MC68020CRC20E Freescale Semiconductor, MC68020CRC20E Datasheet - Page 110

• Manufacturer Part Number: MC68020CRC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020CRC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

5.7.1 MC68020 Bus Arbitration
The sequence of the MC68020 bus arbitration protocol is as follows:
BR may be issued any time during a bus cycle or between cycles. BG is asserted in
response to B R; it is usually asserted as soon as BR has been synchronized and
recognized, except when the MC68020 has made an internal decision to execute a bus
cycle. Then, the assertion of BG is deferred until the bus cycle has begun. Additionally, BG
is not asserted until the end of a read-modify-write operation (when RMC is negated) in
response to a BR signal. When the requesting device receives BG and more than one
external device can be bus master, the requesting device should begin whatever
arbitration is required. The external device asserts BGACK when it assumes bus
mastership, and maintains BGACK during the entire bus cycle (or cycles) for which it is
bus master. The following conditions must be met for an external device to assume
mastership of the bus through the normal bus arbitration procedure:
Figure 5-42 is a flowchart of MC68020 bus arbitration for a single device. Figure 5-43 is a
timing diagram for the same operation. This technique allows processing of bus requests
during data transfer cycles.
MOTOROLA
1. An external device asserts the BR signal.
2. The processor asserts the BG signal to indicate that the bus will become available at
3. The external device asserts the BGACK signal to indicate that it has assumed bus
• The external device must have received BG through the arbitration process.
• AS must be negated, indicating that no bus cycle is in progress, and the external
• The termination signal (DSACK1/DSACK0) for the most recent cycle must have been
• BGACK must be inactive, indicating that no other bus master has claimed ownership
device must ensure that all appropriate processor signals have been placed in the
high-impedance state (by observing specification #7 in Section 10 Electrical
Specifications).
negated, indicating that external devices are off the bus (optional, refer to 5.7.1.3 Bus
Grant Acknowledge (MC68020)).
of the bus.
the end of the current bus cycle.
mastership.
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M68020 USER’S MANUAL
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