MPC866PCZP100A Freescale Semiconductor, MPC866PCZP100A Datasheet - Page 23

• Manufacturer Part Number: MPC866PCZP100A
• Description: IC MPU POWERQUICC 100MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC866PCZP100A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 100MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor
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B35a A(0:31), BADDR(28:30), and D(0:31)
B35b A(0:31), BADDR(28:30), and D(0:31)
Num
B35 A(0:31), BADDR(28:30) to CS valid, as
B36 A(0:31), BADDR(28:30), and D(0:31)
B37 UPWAIT valid to CLKOUT falling
B38 CLKOUT falling edge to UPWAIT
B39 AS valid to CLKOUT rising edge
B40 A(0:31), TSIZ(0:1), RD/WR, BURST,
B41 TS valid to CLKOUT rising edge (setup
B42 CLKOUT rising edge to TS valid (hold
B43 AS negation to memory controller
The timing for BG input is relevant when the MPC866/859 is selected to work with the external bus arbiter.
is asserted.
read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats, where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of CLKOUT, in which the TA input signal
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
For part speeds above 50 MHz, use 9.80 ns for B11a.
The timing required for BR input is relevant when the MPC866/859 is selected to work with the internal bus arbiter.
For part speeds above 50 MHz, use 2 ns for B17.
For part speeds above 50 MHz, use 2 ns for B19.
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
requested by control bit BST4 in the
corresponding word in the UPM (MIN =
0.25 x B1 – 2.00)
to BS valid, as Requested by BST1 in
the corresponding word in the UPM
(MIN = 0.50 x B1 – 2.00)
to BS valid, as requested by control bit
BST2 in the corresponding word in the
UPM (MIN = 0.75 x B1 – 2.00)
to GPL valid as requested by control bit
GxT4 in the corresponding word in the
UPM (MIN = 0.25 x B1 – 2.00)
edge
valid
= 0.00 x B1 + 7.00)
valid to CLKOUT rising edge (MIN =
0.00 x B1 + 7.00)
time) (MIN = 0.00 x B1 + 7.00)
time) (MIN = 0.00 x B1 + 2.00)
signals negation (MAX = TBD)
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(MIN = 0.00 x B1 + 1.00)
(MIN = 0.00 x B1 + 6.00)
Characteristic
MPC866/MPC859 Hardware Specifications, Rev. 2
Table 9. Bus Operation Timings (continued)
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(MIN
13.20
20.70
5.60
5.60
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
33 MHz
Max
TBD
—
—
—
—
—
—
—
—
—
—
10.50
16.70
4.30
4.30
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
40 MHz
Max
TBD
—
—
—
—
—
—
—
—
—
—
13.00
3.00
8.00
3.00
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
50 MHz
Max
TBD
—
—
—
—
—
—
—
—
—
—
1.80
5.60
9.40
1.80
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
66 MHz
Bus Signal Timing
Max
TBD
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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