MPC866PCZP100A Freescale Semiconductor, MPC866PCZP100A Datasheet

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... The MPC866/859/859DSL provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family. © Freescale Semiconductor, Inc., 2006. All rights reserved. 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table 1 for a 3 ...

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... OAM performance monitoring (PM) support — Multiple APC priority levels available to support a range of traffic pace requirements MPC866/MPC859 Hardware Specifications, Rev Table 1. MPC866 Family Functionality Cache Ethernet Data 10T 8 Kbytes Kbytes Kbytes 1 4 Kbytes 1 4 Kbytes 1 4 Kbytes 2 SCC SMC 10/100 Table 1) Freescale Semiconductor ...

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... Periodic interrupt timer (PIT) — Low-power stop mode — Clock synthesizer — Decrementer and time base from the PowerPC architecture — Reset controller — IEEE 1149.1 test access port (JTAG) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 2 C can be relocated without RAM-based microcode Features 3 ...

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... Two SMCs (serial management channels) (MPC859DSL has one SMC (SMC1) for UART.) — UART — Transparent — General circuit interface (GCI) controller — Can be connected to the time-division multiplexed (TDM) channels MPC866/MPC859 Hardware Specifications, Rev GRACEFUL STOP TRANSMIT ENTER HUNT MODE Freescale Semiconductor , and ...

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... V core and 3.3 V I/O operation with 5-V TTL compatibility; refer to tolerant pins. • 357-pin plastic ball grid array (PBGA) package • Operation up to 133 MHz MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 2 C) port Features Table 6 for a listing of the 5-V 5 ...

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... Time Slot Assigner Time Slot Assigner Serial Interface Figure 1. MPC866P Block Diagram 2. System Interface Unit (SIU) Memory Controller Internal External Bus Interface Bus Interface Unit Unit System Functions PCMCIA/ATA Interface 8-Kbyte 16 Virtual Serial and 2 Independent DMA Channels 2 SMC1 SMC2 SPI I C Freescale Semiconductor ...

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... The MPC859P has a 16-Kbyte instruction cache and a 8-Kbyte data cache. * The MPC859DSL does not contain SMC2 nor the time slot assigner, and provides eight SDMA controllers. Figure 2. MPC859P/859T/MPC859DSL Block Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor † 4-Kbyte Instruction Cache Unified ...

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... T A(min) T j(max) . Maximum temperatures are guaranteed Table 2 shows Value Unit – 0.3 to 4.0 V – 0.3 to 2.0 V – 0.3 to 2.0 V 100 mV GND – 0.3 to VDDH V –55 to +150 °C Table 6. Absolute maximum Value Unit 0 °C 95 °C –40 °C 100 °C Freescale Semiconductor ...

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... Thermal characterization parameter indicating the temperature difference between package top and junction temperature per JEDEC JESD51-2. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Environment Natural Convection Single-layer board (1s) Four-layer board (2s2p) Airflow (200 ft/min) ...

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... Symbol VDDL (core) VDDH (I/O) 1 VDDSYN Difference between VDDL to VDDSYN VIH ) Typical Maximum Unit 110 140 mW 150 180 mW 140 160 mW 170 200 mW 210 250 mW 260 320 mW Min Max 1.7 1.9 3.135 3.465 1.7 1.9 — 100 2.0 3.465 Freescale Semiconductor Unit ...

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... PD4/REJECT3, PD3, MII_MDC, MII_TX_ER, MII_EN, MII_MDIO, MII_TXD[0:3]. 5 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD, WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30). MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Symbol VIL VIHC ...

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... It has been observed that the thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see MPC866/MPC859 Hardware Specifications, Rev °C can be obtained from the equation For instance, the user can change the airflow around the device, add a θCA Figure 3. Freescale Semiconductor ...

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... When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor model can be used with the thermal simulation of the application [2 more accurate and complex model of the package can be used in the thermal simulation. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Thermal Calculation and Measurement 13 ...

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... C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54 Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. MPC866/MPC859 Hardware Specifications, Rev Freescale Semiconductor ...

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... At a minimum, a four-layer board employing two inner layers as V All output pins on the MPC866/859 have fast rise and fall times. Printed-circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor (GND). SS VDDH ...

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... GND circuits. Pull up all unused DD 66 MHz Min Max 40 66.67 40 66.67 100 MHz 133 MHz Max Min Max 100 40 133. 66.67 50 MHz 66 MHz Max Min Max Min Max — — — — — +2 – – — 1 — 1 0.50 — 0.50 — 0.50 Freescale Semiconductor Unit ...

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... B11 CLKOUT to TS, BB assertion (MAX = 0. 6.0) B11a CLKOUT to TA, BI assertion (when driven by the memory controller or PCMCIA interface) (MAX = 0. 9.30 ) B12 CLKOUT to TS, BB negation (MAX = 0. 4.8) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz 40 MHz Min Max Min — 4 — — ...

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... Freescale Semiconductor Unit ...

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... CSNT = 1, ACS = 10 or ACS = 11, EBDF = 0 (MAX = 0. 6.80) B28c CLKOUT falling edge to WE(0:3) negated GPCM write access TRLX = 0, CSNT = 1 write access TRLX = 0,1, CSNT = 1, EBDF = 1 (MAX = 0.375 6.6) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz 40 MHz Min Max Min 7.60 13 ...

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... Freescale Semiconductor Unit ...

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... CST2 in the corresponding word in the UPM (MAX = 0. 8.00) B31c CLKOUT rising edge to CS valid, as requested by control bit CST3 in the corresponding word in the UPM (MAX = 0. 6.30) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz 40 MHz Min Max Min 5.60 — ...

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... Freescale Semiconductor Unit ...

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... DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) 7 The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 9. Bus Operation Timings (continued) 33 MHz 40 MHz ...

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... Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification MPC866/MPC859 Hardware Specifications, Rev 0 2.0 V 2.0 V 0 2.0 V 2.0 V 0 2.0 V 2.0 V 0 2.0 V 0.8 V Figure 5. Control Timing Figure 20. 2 2.0 V 0.8 V Freescale Semiconductor ...

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... CLKOUT Figure 7 shows the timing for the synchronous output signals. CLKOUT B7 Output Signals B7a Output Signals B7b Output Signals Figure 7. Synchronous Output Signals Timing MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Figure 6. External Clock Timing B8 B9 B8a B9 B8b Bus Signal Timing B2 25 ...

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... Figure 8. Synchronous Active Pull-Up Resistor and Open-Drain Output Signals Timing Figure 9 shows the timing for the synchronous input signals. CLKOUT TA, BI TEA, KR, RETRY, CR BB, BG, BR Figure 9. Synchronous Input Signals Timing MPC866/MPC859 Hardware Specifications, Rev B11 B12 B11a B12a B14 B15 B16 B17 B16a B17a B16b B17 B13 B13a Freescale Semiconductor ...

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... RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) CLKOUT TA D[0:31], DP[0:3] Figure 11. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1 MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor B16 B17 B18 B19 B20 B21 Bus Signal Timing ...

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... GPCM factors. CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC866/MPC859 Hardware Specifications, Rev B11 B12 B8 B22 B25 B28 B18 B23 B26 B19 Freescale Semiconductor ...

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... D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 11) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor B11 B12 B8 B22a B24 B25 B18 B11 B12 B8 B22b B22c ...

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... Bus Signal Timing CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 15. External Bus Read Timing (GPCM Controlled—TRLX = ACS = 10, ACS = 11) MPC866/MPC859 Hardware Specifications, Rev B12 B8 B22a B27 B27a B22b B22c B18 B23 B26 B19 Freescale Semiconductor ...

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... GPCM factors. CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = CSNT = 0) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor B11 B12 B8 B22 B25 B26 B8 Bus Signal Timing B30 B23 ...

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... Bus Signal Timing CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) MPC866/MPC859 Hardware Specifications, Rev B11 B12 B8 B22 B28b B28d B25 B26 B28a B28c B8 B30a B30c B23 B29c B29g B29a B29f B9 Freescale Semiconductor ...

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... CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 18. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor B12 B8 B22 B28b B28d B25 B26 B8 B28a B28c Bus Signal Timing B30b B30d B23 B29e B29i B29d B29h B29b ...

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... UPM. CLKOUT B8 A[0:31] CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 19. External Bus Timing (UPM Controlled Signals) MPC866/MPC859 Hardware Specifications, Rev B31a B31d B31 B34 B34a B34b B32a B32d B32 B35 B36 B35a B35b B33 B31c B31b B32c B32b B33a Freescale Semiconductor ...

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... Figure 21 shows the timing for the asynchronous negated UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 21. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor B38 B38 Bus Signal Timing 35 ...

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... Bus Signal Timing Figure 22 shows the timing for the synchronous external master access controlled by the GPCM. CLKOUT TS A[0:31], TSIZ[0:1], R/W, BURST CSx Figure 22. Synchronous External Master Access Timing (GPCM Handled ACS = 00) MPC866/MPC859 Hardware Specifications, Rev B41 B42 B40 B22 Freescale Semiconductor ...

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... The timings I41, I42, and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no direct relation with the total system interrupt latency that the MPC866/859 is able to support. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor B39 B40 B43 Table 10 ...

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... I42 50 MHz 66 MHz Unit Max Min Max — 9.40 — ns — 13.20 — ns 13.00 3.80 11.80 ns — 4.80 — ns 13.00 3.80 11.80 ns 13.00 3.80 11.80 ns Freescale Semiconductor ...

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... These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only detected 2 cycles before the PSL timer expiration. See PCMCIA Interface in the MPC866 PowerQUICC User’s Manual . MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 11. PCMCIA Timing (continued) 33 MHz 40 MHz ...

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... PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 27. PCMCIA Access Cycles Timing External Bus Read MPC866/MPC859 Hardware Specifications, Rev P44 P46 P45 P48 P50 P52 P53 B18 P47 P49 P51 P52 B19 Freescale Semiconductor ...

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... PCWE, IOWR ALE D[0:31] Figure 28. PCMCIA Access Cycles Timing External Bus Write Figure 29 shows the PCMCIA WAIT signals detection timing. CLKOUT WAITx Figure 29. PCMCIA WAIT Signals Detection Timing MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor P44 P46 P45 P48 P50 P52 P53 B8 P55 ...

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... Figure 30. PCMCIA Output Port Timing P59 P60 Figure 31. PCMCIA Input Port Timing 50 MHz 66 MHz Max Min Max Min Max 19.00 — 19.00 — 19.00 — 18.00 — 14.40 — — 5.00 — 5.00 — — 1.00 — 1.00 — Freescale Semiconductor Unit ...

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... DSCK Figure 33 shows the timing for the debug port. DSCK DSDI DSDO MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 13. Debug Port Timing Characteristic D61 D62 D61 D63 Figure 32. Debug Port Clock Input Timing ...

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... Freescale Semiconductor ...

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... CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak) Figure 35. Reset Timing—Data Bus Weak Drive During Configuration MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor R71 R76 R73 R74 R75 R69 R79 R77 ...

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... Characteristic R81 through Figure 40. All Frequencies Unit Min Max 100.00 — ns 40.00 — ns 0.00 10.00 ns 5.00 — ns 25.00 — ns — 27.00 ns 0.00 — ns — 20.00 ns 100.00 — ns 40.00 — ns — 50.00 ns — 50.00 ns — 50.00 ns 50.00 — ns 50.00 — ns Freescale Semiconductor ...

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... TCK TCK TMS, TDI TDO Figure 38. JTAG Test Access Port Timing Diagram TCK TRST MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor J82 J83 J82 J84 Figure 37. JTAG Test Clock Input Timing J85 J86 J87 J88 J91 J90 Figure 39. JTAG TRST Timing Diagram IEEE 1149 ...

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... Figure 41 through Table 16. PIP/PIO Timing Characteristic J94 J95 J96 Figure 45. All Frequencies Unit Min Max 0 — 2.5 – t3 — clk 1.5 — clk 1 clk – 5ns — — clk 5 — clk — 2 clk 2 — clk 15 — ns 7.5 — ns — Freescale Semiconductor ...

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... DATA-IN STBI STBO Figure 41. PIP Rx (Interlock Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 42. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 43. PIP Rx (Pulse Mode) Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor CPM Electrical Characteristics ...

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... Num 35 Port C interrupt pulse width low (edge-triggered mode) 36 Port C interrupt minimum time between active edges Figure 46 shows the port C interrupt detection timing. MPC866/MPC859 Hardware Specifications, Rev Table 17. Port C Interrupt Timing Characteristic 26 30 33.34 MHz Unit Min Max 55 — — ns Freescale Semiconductor ...

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... SDACK negation delay from clock high 46 TA assertion to falling edge of the clock setup time (applies to external TA) CLKO (Output) DREQ (Input) Figure 47. IDMA External Requests Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 35 Figure 46. Port C Interrupt Detection Timing Figure 47 Table 18. IDMA Controller Timing Characteristic 40 CPM Electrical Characteristics 36 ...

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... CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 48. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 49. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA MPC866/MPC859 Hardware Specifications, Rev Freescale Semiconductor ...

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... Num 50 BRGO rise and fall time 51 BRGO duty cycle 52 BRGO cycle 50 BRGOX Figure 51. Baud Rate Generator Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 42 Figure 51. Table 19. Baud Rate Generator Timing Characteristic CPM Electrical Characteristics 45 All Frequencies ...

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... MPC866/MPC859 Hardware Specifications, Rev Figure 52. Table 20. Timer Timing Characteristic Figure 53 through Table 21. SI Timing All Frequencies Min 1, 2 — — 20.00 All Frequencies Unit Min Max 10 — — clk 2 — clk 3 — clk Figure 57. Unit Max SYNCCLK/2.5 MHz — ns — ns 15.00 ns — ns Freescale Semiconductor ...

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... These specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate ns. 4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 21. SI Timing (continued) All Frequencies Min 35.00 — ...

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... CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) 71 L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1RXD (Input) L1ST(4-1) (Output) Figure 53. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC866/MPC859 Hardware Specifications, Rev 71a 72 RFSD BIT0 Freescale Semiconductor ...

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... L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 54. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 72 83a RFSD=1 77 BIT0 78 84 CPM Electrical Characteristics 79 57 ...

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... CPM Electrical Characteristics L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) L1TXD (Output) L1ST(4-1) (Output) Figure 55. SI Transmit Timing Diagram (DSC = 0) MPC866/MPC859 Hardware Specifications, Rev TFSD 80a BIT0 Freescale Semiconductor ...

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... L1RCLK (FE=0, CE=0) (Input) L1RCLK (FE=1, CE=1) (Input) 75 L1RSYNC (Input) 73 L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 56. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 72 83a 82 TFSD CPM Electrical Characteristics 79 59 ...

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... CPM Electrical Characteristics MPC866/MPC859 Hardware Specifications, Rev Figure 57. IDL Timing Freescale Semiconductor ...

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... The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1. 2 Also applies to CD and CTS hold time when they are used as an external sync signals. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 22. NMSI External Clock Timings Characteristic 1 2 Table 23. NMSI Internal Clock Timings ...

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... Figure 58. SCC NMSI Receive Timing Diagram TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Input) CTS1 (SYNC Input) Figure 59. SCC NMSI Transmit Timing Diagram MPC866/MPC859 Hardware Specifications, Rev 102 101 100 107 102 101 100 103 105 104 108 107 104 107 Freescale Semiconductor ...

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... TCLK1 clock period 131 TXD1 active delay (from TCLK1 rising edge) 132 TXD1 inactive delay (from TCLK1 rising edge) 133 TENA active delay (from TCLK1 rising edge) MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 102 101 100 103 104 107 105 Figure 60. HDLC Bus Timing Diagram ...

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... RCLK1 RxD1 (Input) RENA(CD1) (Input) Figure 62. Ethernet Receive Timing Diagram MPC866/MPC859 Hardware Specifications, Rev Table 24. Ethernet Timing (continued) Characteristic 2 2 120 121 124 125 All Frequencies Unit Min Max — CLK — — 121 123 Last Bit 126 127 Freescale Semiconductor ...

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... RSTRT (Output) Figure 64. CAM Interface Receive Start Timing Diagram REJECT Figure 65. CAM Interface REJECT Timing Diagram 12.9 SMC Transparent AC Electrical Specifications Table 25 shows the SMC transparent timings as shown in MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 128 121 132 1 1 BIT1 125 137 Figure 66 ...

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... This delay is equal to an integer number of character-length clocks. Figure 66. SMC Transparent Timing Diagram MPC866/MPC859 Hardware Specifications, Rev Table 25. SMC Transparent Timing Characteristic 1 152 151 151A 150 NOTE 1 154 155 155 All Frequencies Unit Min Max 100 — — — ns — — — ns 153 Freescale Semiconductor ...

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... SPICLK (CI=1) (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI msb (Output) Figure 67. SPI Master ( Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Figure 67 and Figure Table 26. SPI Master Timing Characteristic 167 166 160 167 166 Data lsb 165 164 ...

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... MPC866/MPC859 Hardware Specifications, Rev 167 166 160 167 166 Data lsb 165 164 Data Figure 69 and Figure Table 27. SPI Slave Timing Characteristic msb 166 lsb msb 70. All Frequencies Unit Min Max 2 — t cyc 15 — — — t cyc 1 — t cyc 20 — — ns — Freescale Semiconductor ...

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... SPICLK (CI=1) (Input) 177 SPIMISO msb (Output) 175 176 SPIMOSI msb (Input) Figure 69. SPI Slave ( Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 172 182 181 170 181 182 180 Data lsb 179 181 182 Data lsb CPM Electrical Characteristics ...

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... SPIMISO Undef (Output) 175 SPIMOSI (Input) Figure 70. SPI Slave ( Timing Diagram 12.12I Electrical Specifications MPC866/MPC859 Hardware Specifications, Rev 172 170 182 181 181 182 180 msb Data 179 176 181 182 msb Data 174 178 msb lsb msb lsb Freescale Semiconductor ...

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... SDL/SCL fall time 211 Stop condition setup time 1 SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2). The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1. MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor 2 Table 28 Timing (SCL < 100 kHz) Characteristic 1 2 Table 29 Timing (SCL > 100 kHz) ...

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... MPC866/MPC859 Hardware Specifications, Rev 204 207 209 210 2 Figure 71 Bus Timing Diagram Direction Direction 208 211 Min Max Unit Output — — 33 MHz Output Input 4 — ns Input 1 — ns Min Max Unit Output — — 33 MHz Output Input 4 — ns Input 1 — ns Freescale Semiconductor ...

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... UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr hold time Figure 72 shows signal timings during UTOPIA receive operations. UtpClk U2 PHREQn RxClav HighZ at MPHY RxEnb UTPB SOC MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Direction Figure 72. UTOPIA Receive Timing UTOPIA AC Electrical Specifications Min Max Unit Input — ...

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... MII_RX_CLK pulse width low Figure 74 shows the timings for MII receive signal. MPC866/MPC859 Hardware Specifications, Rev Figure 73. UTOPIA Transmit Timing Table 33. MII Receive Signal Timing Characteristic High-Z at MPHY Min Max Unit 5 — — ns 35% 65% MII_RX_CLK period 35% 65% MII_RX_CLK period Freescale Semiconductor ...

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... MII transmit signal timing. Num Characteristic M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid M7 MII_TX_CLK pulse width high M8 MII_TX_CLK pulse width low MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 34. MII Transmit Signal Timing FEC Electrical Characteristics Min Max Unit 5 — ns — ...

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... MII_MDC falling edge to MII_MDIO output valid (maximum propagation delay) M12 MII_MDIO (input) to MII_MDC rising edge setup MPC866/MPC859 Hardware Specifications, Rev Table 35. MII Async Inputs Signal Timing Characteristic M9 Characteristic Min Max Unit 1.5 — MII_TX_CLK period Min Max Unit 0 — ns — — ns Freescale Semiconductor ...

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... MII_MDC pulse width low Figure 77 shows the MII serial management channel timing diagram. MII_MDC (output) MII_MDIO (output) MII_MDIO (input) Figure 77. MII Serial Management Channel Timing Diagram MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Characteristic M14 MM15 M10 M11 M12 M13 FEC Electrical Characteristics ...

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... Cache Size Instruction Data 4 Kbyte 4 Kbytes 16 Kbyte 8 Kbytes 4 Kbyte 4 Kbytes 4 Kbyte 4 Kbytes Order Number MPC859DSLZP50A MPC859DSLZP66A MPC859PZP100A MPC859TZP100A MPC866PZP100A MPC866TZP100A MPC859PZP133A MPC859TZP133A MPC866PZP133A MPC866TZP133A MPC859DSLCZP50A MPC859DSLCZP66A MPC859PCZP100A MPC859TCZP100A MPC866PCZP100A MPC866TCZP100A Freescale Semiconductor ...

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... Table 38. MPC866/859 Package/Frequency Orderable (continued) Plastic ball grid array (VR suffix) Lead free Plastic ball grid array (CVR suffix) Lead free MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Mechanical Data and Ordering Information 0° to 95° 100 133 –40° to 100° 100 ...

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... IPB6 ALEA IRQ4 IPB5 IPB1 IPB2 ALEB M_COL IRQ2 IPB0 IPB7 BR IRQ6 IPB4 IPB3 GND VDDL TS IRQ3 BURST VDDH CS3 CS6 CS2 GPLA5 BDIP TEA WE0 GPLA1 GPLA3 CS7 CS0 TA GPLA4 CS5 CE1A WR GPLB4 WE1 WE3 CS4 CE2A CS1 Freescale Semiconductor ...

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... T13, V13, V10, T10, U10, T12, V9, U9, V8, U8, T9, U12, V7, T8, U7, V12, V6, W5, U6, T7 DP0 V3 IRQ3 DP1 V5 IRQ4 DP2 W4 IRQ5 DP3 V4 IRQ6 MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Mechanical Data and Ordering Information Table 39. Pin Assignments Pin Number Type Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state ...

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... GPL_A[2:3] B5, C5 GPL_B[2:3] CS[2–3] UPWAITA C1 GPL_A4 MPC866/MPC859 Hardware Specifications, Rev Table 39. Pin Assignments (continued) Pin Number Type Bidirectional Bidirectional Bidirectional Active Pull-up Bidirectional Input Input Input Output Output Output Output Output Output Output Output Output Output Output Bidirectional Freescale Semiconductor ...

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... UTPB_Split2 MII-RXD1 IP_A3 W2 2 UTPB_Split3 MII-RXD0 IP_A4 U4 2 UTPB_Split4 MII-RXCLK MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 39. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional Output Input Input Open-drain Open-drain Analog Output Analog Input (3.3V only) Output Input (3 ...

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... IP_B7 H1 PTR AT3 OP0 L4 MII-TXD0 2 UtpClk_Split OP1 L2 OP2 L1 MODCK1 STS MPC866/MPC859 Hardware Specifications, Rev Table 39. Pin Assignments (continued) Pin Number Type Input Input Input Bidirectional Three-state Bidirectional Bidirectional Three-state Bidirectional Bidirectional Bidirectional Bidirectional Three-state Bidirectional Three-state Bidirectional Output Bidirectional Freescale Semiconductor ...

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... L17 L1RXDA TXD4 PA7 M19 CLK1 L1RCLKA BRGO1 TIN1 PA6 M17 CLK2 TOUT1 MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 39. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional Output Output Input Bidirectional Bidirectional (Optional: Open-drain) Bidirectional Bidirectional ...

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... PB26 F19 I2CSCL BRGO2 MPC866/MPC859 Hardware Specifications, Rev Table 39. Pin Assignments (continued) Pin Number Type Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Freescale Semiconductor ...

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... RXADDR4 RTS2 L1ST2 PB17 P18 L1RQb L1ST3 RTS3 1 PHREQ1 2 RXADDR1 MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 39. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional ...

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... RTS4 PC11 J19 CTS1 PC10 K19 CD1 TGATE1 PC9 L18 CTS2 PC8 M18 CD2 TGATE2 MPC866/MPC859 Hardware Specifications, Rev Table 39. Pin Assignments (continued) Pin Number Type Bidirectional (Optional: Open-drain) Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Freescale Semiconductor ...

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... L1RSYNCB MII-MDC UTPB3 PD11 T16 RXD3 MII-TXERR RXENB PD10 W18 TXD3 MII-RXD0 TXENB MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 39. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional ...

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... TCK H16 DSCK TRST G19 TDO G17 DSDO MII_CRS B7 MII_MDIO H18 MII_TXEN V15 MPC866/MPC859 Hardware Specifications, Rev Table 39. Pin Assignments (continued) Pin Number Type Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Input Input Input Input Output Input Bidirectional Output Freescale Semiconductor ...

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... P15, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, T14 N/C D6, D13, D14, U2, V2 Classic SAR mode only 2 ESAR mode only MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 39. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Input PLL analog VDD and GND ...

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... Freescale sales office. Note: Solder sphere composition for MPC866XZP, MPC859PZP, MPC859DSLZP, and MPC859TZP is 62%Sn 36%Pb 2%Ag Figure 79. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC866/MPC859 Hardware Specifications, Rev Figure 79 shows the mechanical dimensions of the PBGA package. Freescale Semiconductor ...

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... MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Table 40. Document Revision History Substantive Changes • Added TxClav and RxClav to PB15 and PC15. Changed B28a through B28d and B29b to show that TRLX can • Added nontechnical reformatting. • Updated document template. ...

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... Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC866/MPC859 Hardware Specifications, Rev Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC866/MPC859 Hardware Specifications, Rev. 2 Freescale Semiconductor Document Revision History 95 ...

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... All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical ...