MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 29

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SECTION 3
SIGNAL DESCRIPTION
This section contains descriptions of the input and output signals. The input and output
signals can be functionally organized into the groups shown in Figure 3-1 (for the
MC68000, the MC68HC000 and the MC68010), Figure 3-2 ( for the MC68HC001), Figure
3-3 (for the MC68EC000), Figure 3-4 (for the MC68008, 48-pin version), and Figure 3-5
(for the MC68008, 52-pin version). The following paragraphs provide brief descriptions of
the signals and references (where applicable) to other paragraphs that contain more
information about the signals.
MOTOROLA
The terms assertion and negation are used extensively in this
manual to avoid confusion when describing a mixture of
"active-low" and "active-high" signals. The term assert or
assertion is used to indicate that a signal is active or true,
independently of whether that level is represented by a high or
low voltage. The term negate or negation is used to indicate
that a signal is inactive or false.
PROCESSOR
PERIPHERAL
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
CONTROL
CONTROL
SYSTEM
STATUS
MC6800
(MC68000, MC68HC000 and MC68010)
Figure 3-1. Input and Output Signals
GND(2)
RESET
V CC (2)
BERR
HALT
VMA
VPA
CLK
FC0
FC1
FC2
E
NOTE
ADDRESS
DATA BUS
BUS
BR
AS
R/W
UDS
LDS
DTACK
BG
BGACK
IPL0
IPL1
IPL2
A23–A1
D15–D0
ASYNCHRONOUS
BUS
CONTROL
BUS
ARBITRATION
CONTROL
INTERRUPT
CONTROL
3- 1