MC68HC000RC12 Freescale Semiconductor, MC68HC000RC12 Datasheet - Page 25

• Manufacturer Part Number: MC68HC000RC12
• Description: IC MPU 32BIT 12MHZ 68-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC000RC12

• Processor Type: M680x0 32-Bit
• Speed: 12MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 16/32Bit
• Frequency (max): 12MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 68
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
ANDI to CCR Source
ANDI to SR
ASL, ASR
Opcode
ADDQ
BCHG
CMPA
CMPM
ABCD
ADDA
ADDX
BCLR
BKPT
BSET
ADDI
ANDI
BTST
CMPI
DBcc
CMP
ADD
AND
BRA
BSR
CHK
CLR
Bcc
Source 10 + Destination 10 + X
Source + Destination
Source + Destination
Immediate Data + Destination
Immediate Data + Destination
Source + Destination + X
Source
Immediate Data
If supervisor state
else TRAP
If (condition true) then PC + d
~ (<number> of Destination)
~ (<number> of Destination)
~ (<bit number> of Destination)
0
Run breakpoint acknowledge cycle;
TRAP as illegal instruction
PC + d
~ (<bit number> of Destination)
1
SP – 4
– (<bit number> of Destination)
If Dn < 0 or Dn > Source then TRAP
0
Destination—Source
Destination—Source
Destination —Immediate Data
Destination—Source
If condition false then (Dn – 1
If Dn –1 then PC + d
Destination Shifted by <count>
then Source
<bit number> of Destination
<bit number> of Destination
Destination
M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL
Table 2-2. Instruction Set Summary (Sheet 1 of 4)
CCR
PC
SP; PC
Destination
SR
CCR
Destination
(SP); PC + d
SR
Destination
Destination
cc
cc
PC)
Operation
Destination
Destination
Z;
<bit number> of Destination
PC
Dn;
Destination
Destination
Destination
Destination
Z;
Z;
Z;
Destination
PC
CMPI # <data>,<ea>
ABCD Dy,Dx
ADDI # <data>,<ea>
CHK <ea>,Dn
ABCD –(Ay), –(Ax)
ADD <ea>,Dn
ADD Dn,<ea>
ADDA <ea>,An
ADDQ # <data>,<ea>
ADDX Dy, Dx
ADDX –(Ay), –(Ax)
AND <ea>,Dn
AND Dn,<ea>
ANDI # <data>, <ea>
ANDI # <data>, CCR
ANDI # <data>, SR
ASd Dx,Dy
ASd # <data>,Dy
ASd <ea>
Bcc <label>
BCHG Dn,<ea>
BCHG # <data>,<ea>
BCLR Dn,<ea>
BCLR # <data>,<ea>
BKPT # <data>
BRA <label>
BSET Dn,<ea>
BSET # <data>,<ea>
BSR <label>
BTST Dn,<ea>
BTST # <data>,<ea>
CLR <ea>
CMP <ea>,Dn
CMPA <ea>,An
CMPM (Ay)+, (Ax)+
DBcc Dn,<label>
S y n t a x
2-11