MC68EC030CFE25C Freescale Semiconductor, MC68EC030CFE25C Datasheet - Page 157
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MC68EC030CFE25C
Manufacturer Part Number
MC68EC030CFE25C
Description
IC MPU 32BIT ENH 25MHZ 132-CQFP
Manufacturer
Freescale Semiconductor
Specifications of MC68EC030CFE25C
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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Quantity
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6.2 CACHE RESET
6.3 CACHE C O N TR O L
6.3.1 Cache Control Register
6-20
the cache control register (CACR) for both caches (refer to Figure 6-14) are
The CACR, shown in Figure 6-14, is a 32-bit register that can be written or
during the second, third, or fourth cycle of a burst operation does not cause
When a hardware reset of the processor occurs, all valid bits of both caches
are cleared. The cache enable bits, burst enable bits, and the freeze bits in
also cleared, effectively disabling both caches. The WA bit in the CACR is
also cleared.
Only the MC68030 cache control circuitry can directly access the cache arrays,
cache operations. The supervisor also has access to the cache address reg-
cache. Each cache is controlled independently of the other, although a similar
operation can be performed for both caches by a single MOVEC instruction.
On the initial access of a burst operation, a "retry" (indicated by the assertion
of BERR and HAL-I = ) causes the processor to retry the bus cycle and assert
CBREQ again. However, signaling a retry with simultaneous BERR and HALT
a retry operation, even if the requested operand is misaligned. Assertion of
BERR and HALT during burst fill cycles of a burst operation causes inde-
pendent bus error and halt operations. The processor remains halted until
HALT is negated, and then handles the bus error as described in the previous
paragraphs.
but the supervisor program can set bits in the CACR to exercise control over
ister (CAAR), which contains the address for a cache entry to be cleared.
read by the MOVEC instruction or indirectly modified by a reset. Five of the
bits (4-0) control the instruction cache; six other bits (13-8) control the data
For example, loading a long word in which bits 3 and 1 1 a r e set into the
CACR clears both caches. Bits 31-14 and 7-5 are reserved for Motorola
definition. They are currently read as zeros and are ignored when written.
For future compatibility, writes should not set these bits.
MC68030 USER'S MANUAL
MOTOROLA
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