MC68EC030CFE25C Freescale Semiconductor, MC68EC030CFE25C Datasheet - Page 151
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MC68EC030CFE25C
Manufacturer Part Number
MC68EC030CFE25C
Description
IC MPU 32BIT ENH 25MHZ 132-CQFP
Manufacturer
Freescale Semiconductor
Specifications of MC68EC030CFE25C
Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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Available stocks
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Manufacturer
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Part Number:
MC68EC030CFE25C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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6
6-14
CYCLE
2
3
4
1
The next example, shown in Figure 6-9, is a read of a misaligned long-word
the second long-word cache entry.
Two read cycles are required for a misaligned long-word operand transfer
from devices that return 32-bit DSACKx encodings. As shown in Figure 6-10,
the first read cycle requests the long word at address $06 and latches the
cycles are also required if STERM is used to indicate a 32-bit port instead of
the 32-bit DSACKx encoding.
operand from devices that return 16-bit DSACKx encodings. The processor
accepts the first portion of the operand, the word from address $06, and
it in the cache also. Finally, the processor accesses the word at $0A to fill
long word at address $04. The second read cycle requests and latches the
long word corresponding to the second cache entry at address $08. Two read
requests a word from address $04 to fill the cache entry. Next, the processor
reads the word at address $08, the second portion of the operand, and stores
LON6 WORD
WORD
WORD
WORD
SIZE
ADDRESS
$OA
$06
$04
$08
$00
Figure 6-9. Single Entry Mode Operation - -
Misaligned Long Word and 16-Bit Port
MC68030 USER'S MANUAL
$04
E E l
$08
~ ]
- FIRST WORD OF OPERANO LATCHED
- TO FILL THE CACHE ENTRY AT$04
- SECOND WORD OF OPERAND
- TO FILL ENTRY AT $08
$OC
COMMENT
MOTOROLA
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