MPC8358EZQAGDGA Freescale Semiconductor, MPC8358EZQAGDGA Datasheet - Page 75

• Manufacturer Part Number: MPC8358EZQAGDGA
• Description: MPU POWERQUICC II PRO 668-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8358EZQAGDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 668-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock
divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock
divider ratio is controlled by LCRR[CLKDIV].
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
frequency.
Table 67
conditions (see
Maximum operating frequencies depend on the part ordered, see
Addressed by this Document,”
authorized distributor for more information.
Freescale Semiconductor
1
2
3
e300 core frequency ( core_clk )
Coherent system bus frequency
( csb_clk )
QUICC Engine frequency
( ce_clk )
DDR and DDR2 memory bus frequency
(MCLK)
Local bus frequency
(LCLK n )
PCI input frequency (CLKIN or PCI_CLK)
Security core maximum internal operating frequency
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk ,
MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
The DDR data rate is 2x the DDR memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1x or 2x
the csb_clk frequency (depending on RCWL[LBCM]).
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
2
provides the operating frequencies for the PBGA package under recommended operating
3
Table
1
Security core
PCI and DMA complex
With limitation, only for slow csb_clk rates, up to 166 MHz.
2). All frequency combinations shown in the table below may not be available.
Table 67. Operating Frequencies for the PBGA Package
Unit
Characteristic
for part ordering details and contact your Freescale sales representative or
Table 66. Configurable Clock Units
1
Table 66
Frequency
csb_clk
Default
csb_clk
specifies which units have a configurable clock
/3
Off,
csb_clk
Off,
csb_clk
csb_clk
Section 25.1, “Part Numbers Fully
/3
1
Options
, csb_clk
16.67–133
25–66.67
400 MHz
266–400
133–266
266–400
100–133
133
/2,
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Clocking
75