MC68030FE16C Freescale Semiconductor, MC68030FE16C Datasheet - Page 164
MC68030FE16C
Manufacturer Part Number
MC68030FE16C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68030FE20C.pdf
(599 pages)
Specifications of MC68030FE16C
Processor Type
M680x0 32-Bit
Speed
166MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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7.1.1 Bus Control Signals
MOTOROLA
A device with a 32-bit port size can also provide a synchronous mode transfer.
while address strobe (AS) is asserted), regardless of when the signals are
MC68030 E/ectrica/ Specifications).
Synchronous inputs (STERM, CBACK, and ClIN) must remain stable during
a sample window for all rising edges of the clock during a bus cycle (i.e.,
asserted or negated, to ensure proper operation. This sample window is
defined by the synchronous input setup and hold times (see MC68030EC/D,
The external cycle start (ECS) signal is the earliest indication that the pro-
the address, size, function code, read/write, and cache inhibit-out outputs
In synchronous operation, input signals are externally synchronized to the
processor clock, and the synchronizing delay is not incurred.
cessor is initiating a bus cycle. The MC68030 initiates a bus cycle by driving
and by asserting ECS. However, if the processor finds the required program
or data item in an on-chip cache, if a miss occurs in the address translation
cache (ATC) of the memory management unit (MMU), or if the MMU finds
a fault with the access, the processor aborts the cycle before asserting AS.
ECS can be used to initiate various timing sequences that are eventually
qualified with AS. Qualification with AS may be required since, in the case
of an internal cache hit, an ATC miss, or an MMU fault, a bus cycle may be
aborted after ECS has been asserted. The assertion of AS ensures that the
cycle has not been aborted by these internal conditions.
start (OCS) signal is asserted with ECS. When several bus cycles are required
During the first external bus cycle of an operand transfer, the operand cycle
C L K
E X T
Figure 7-2. Asynchronous Input Sample Window
MC68030 USER'S MANUAL
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