MPC8343CVRAGDB Freescale Semiconductor, MPC8343CVRAGDB Datasheet - Page 72

• Manufacturer Part Number: MPC8343CVRAGDB
• Description: IC MPU PWRQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8343CVRAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• For Use With: CWH-PPC-8343N-VX - KIT EVAL SYSTEM QUICCSTART 8248CWH-PPC-8343N-VE - EVALUATION SYSTEM QUICC MPC8343E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

System Design Information
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8343EA.
21.1
The MPC8343EA includes two PLLs:
21.2
Each PLL gets power through independent power supply pins (AV
level should always equal to V
low frequency filter scheme.
There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to
provide four independent filter circuits as illustrated in
Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.
The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built
with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value
capacitor.
To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the
specific AV
pin, which is on the periphery of package, without the inductance of vias.
Figure 37
72
1. The platform PLL generates the platform clock from the externally supplied CLKIN input. The
2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
R
P
frequency ratio between the platform and CLKIN is selected using the platform PLL ratio
configuration bits as described in
between the e300 core clock and the platform clock is selected using the e300 PLL ratio
configuration bits as described in
θ
D
System Clocking
PLL Power Supply Filtering
JC
shows the PLL power supply filter circuit.
= power dissipation (W)
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 10
DD
= junction-to-case thermal resistance (°C/W)
pin being supplied. It should be possible to route directly from the capacitors to the AV
V
DD
DD
Figure 37. PLL Power Supply Filter Circuit
10 Ω
, and preferably these voltages are derived directly from V
2.2 µF
Section 19.1, “System PLL Configuration.”
Section 19.2, “Core PLL Configuration.”
GND
Low ESL Surface Mount Capacitors
Figure
2.2 µF
37, one to each of the four AV
DD
AV
1, AV
DD
(or L2AV
DD
2, respectively). The AV
DD
)
Freescale Semiconductor
DD
DD
through a
pins.
DD
DD