MC68EC000EI20 Freescale Semiconductor, MC68EC000EI20 Datasheet - Page 12
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MC68EC000EI20
Manufacturer Part Number
MC68EC000EI20
Description
IC MPU 32BIT 20MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Specifications of MC68EC000EI20
Processor Type
M680x0 32-Bit
Speed
20MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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SECTION 1
INTRODUCTION
This manual contains detailed information about software instructions used by the
microprocessors and coprocessors in the M68000 family, including:
The M68000 family programming model consists of two register groups: user and
supervisor. User programs executing in the user mode only use the registers in the user
group. System software executing in the supervisor mode can access all registers and uses
the control registers in the supervisor group to perform supervisor functions. The following
paragraphs provide a brief description of the registers in the user and supervisor models as
well as the data organization in the registers.
MOTOROLA
MC68000
MC68EC000
MC68HC000
MC68008
MC68010
MC68020
MC68EC020
MC68030
MC68EC030
MC68040
MC68LC040
MC68EC040
MC68330
MC68340
MC68851
MC68881
MC68882
All references to the MC68000, MC68020, and MC68030
include the corresponding embedded controllers, MC68EC000,
MC68EC020, and MC68EC030. All references to the MC68040
include the MC68LC040 and MC68EC040. This referencing
method applies throughout the manual unless otherwise
specified.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16-/32-Bit Microprocessor
16-/32-Bit Embedded Controller
Low Power 16-/32-Bit Microprocessor
16-Bit Microprocessor with 8-Bit Data Bus
16-/32-Bit Virtual Memory Microprocessor
32-Bit Virtual Memory Microprocessor
32-Bit Embedded Controller
Second-Generation 32-Bit Enhanced Microprocessor
32-Bit Embedded Controller
Third-Generation 32-Bit Microprocessor
Third-Generation 32-Bit Microprocessor
32-Bit Embedded Controller
Integrated CPU32 Processor
Integrated Processor with DMA
Paged Memory Management Unit
Floating-Point Coprocessor
Enhanced Floating-Point Coprocessor
NOTE
1-1
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