Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 95

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ON-CHIP PERIPHERAL FUNCTIONS
The Z380 MPU incorporates a number of functions to ease
its interface with external I/O devices and with various
types of memories. The Z380 MPU's I/O bus can be
programmed to run at a slower rate than its memory bus.
In addition, a heartbeat transaction can be generated on
the I/O bus that emulates a Z80 CPU instruction fetch
cycle. Such a transaction is useful for a particular Z80
family I/O device to perform its interrupt functions. Memory
chip select signals can be activated to access the lowest
16 Mbytes of the Z380 MPU's memory address space, with
wait state insertions. Lastly, a DRAM refresh function is
incorporated, with programmable refresh transaction burst
size. The above functions are controlled by several on-
chip registers. As described in the CPU Architecture
section, these registers together with several other regis-
ters that control a portion of the interrupt functions, occupy
an on-chip I/O address space. This on-chip I/O address
can be accessed only by the following reserved on-chip
I/O instructions.
Some on-chip peripherals are capable of generating inter-
rupt requests, which are always handled in the assigned
interrupt vectors mode.
I/O Bus Control
The Z380 MPU is designed to interface easily with external
I/O devices that can be of either the Z80 or Z8500 product
family by supplying five I/O bus control signals: /M1,
/IORQ, /IORD, /IOWR and /INTAK. In addition, the Z380
MPU is supplying an IOCLK that is a divided down version
of its BUSCLK. Programmable wait states can be inserted
in the various I/O transactions. The External Interface
section details all the I/O transactions.
7
IOCR0: 00000011H
R/W
- -
0
- -
0
- -
0
Figure 28. I/O Bus Control Register 0
- -
0
0
- -
CR2
0
CR1 CR0
0
When one of the above instructions is executed, the Z380
MPU outputs the register address being accessed in a
pseudo transaction of two BUSCLK cycles duration, with
the address signals A31-A8 at logic 0s. In the pseudo
transaction, all bus control signals are at their inactive
states. It is to be emphasized that the Z380 MPU adopts an
instruction specific scheme to access on-chip I/O regis-
ters, with their unique address space. This is in contrast to
mapping such registers with external peripherals in a
common I/O address space, as is done in the Z180 MPU.
I/O Bus Control Register 0
CR2-CR0 (I/O Clock Rate). BUSCLK is divided down to
produce IOCLK as defined in the following.
Note that if a clock divide rate of 1 is specified, BUSCLK
should be used to connect to I/O devices that require a
clock input, since the Z380 MPU outputs a constant logic
1 at IOCLK.
Reserved bits 7-3. Read as 0s, should write to as 0s.
000
010
100
110
IN0
IN0
OUT0
TSTIO
0
0
divided-by-8
divided-by-2
divided-by-4
divided-by-6
<- Reset Value
Reserved Program as 0
Read as 0
I/O Clock
R, (n)
(n)
(n), R
n
001
011
101
111
Page 95 of 125
OTIM
OTIMR
OTDM
OTDMR
divided-by-1
divided-by-1
divided-by-1
divided-by-1