Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 35
Z8038018FSG
Manufacturer Part Number
Z8038018FSG
Description
IC 16 BIT Z80 MPU 100-QFP
Manufacturer
Zilog
Specifications of Z8038018FSG
Processor Type
Z380
Features
16-Bit, High-Performance Enhanced Z80 CPU
Speed
18MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
100-QFP
Processor Series
Z80380x
Core
Z380
Program Memory Size
64 KB
Maximum Clock Frequency
18 MHz
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PS010002-0708
HALT Transactions
A HALT transaction occurs whenever the Z380 MPU executes a Halt instruction, with the
/HALT signal activated on the falling edge of BUSCLK. If the standby mode is not
enabled, executing a Sleep instruction would also cause a Halt transaction to occur. While
in the Halt state, the Z380 MPU continues to drive the address and data buses, and the
/HALT signal remains active until either an interrupt request is acknowledged or a reset is
received. Refresh transactions may occur while in the halt state and the bus can be granted.
The timing of entry into the Halt state is shown in Figure 24, while the timing of exiting
from Halt state is shown in Figure 25.
ADDRESS
BUSCLK
STATUS
/TREFR
/TREFA
/TREFC
/MSIZE
/HALT
/WAIT
/MWR
DAT A
/MRD
T5
Figure 24. HALT Entry
THL
THH
THL
Z380 Microprocessor
Product Specification
Page 35 of 125
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