Z8018233FSC Zilog, Z8018233FSC Datasheet - Page 79
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Z8018233FSC
Manufacturer Part Number
Z8018233FSC
Description
IC 33MHZ STATIC MIMIC 100-QFP
Manufacturer
Zilog
Datasheet
1.Z8018233FSG.pdf
(109 pages)
Specifications of Z8018233FSC
Processor Type
Z180
Features
Smart Peripheral Controller
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
100-QFP
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Interface Type
UART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018233FSC
Manufacturer:
ZILOG
Quantity:
591
SLEEP, HALT EFFECT ON MIMIC AND 182 SIGNALS
The following Z80182/Z8L182 signals are driven High
when Z180
DS971820600
EMULATION MODES (Continued)
Signal
PHI
/M1
/MREQ,/MRD
/IORQ
/RD
/WR
/RFSH
/HALT
ST
E
/BUSACK
/WAIT
A19,A18/T
A17-A0
D7-D0
TxA0
/RTS0
TxA1
/INT0
Zilog
/MRD when selected in the Interrupt
Edge/Pin MUX Register.
/MWR when selected in the Interrupt
Edge/Pin MUX Register.
/ROMCS,/RAMCS always High in
SLEEP or HALT.
OUT
™
MPU enters a SLEEP or HALT state:
Table 21. Emulation Mode 1
Input/Output
Normal
Mode 0
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Emulation Adaptor
Output, Open-Drain
Input/Output
Tri-state
Tri-state
Tri-state
Tri-state
Mode 1
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
PS009801-0301
P R E L I M I N A R Y
Mode 2 Emulation Probe Mode
In the Emulator Probe Mode all of the Z182 output signals
are tri-state. This scheme allows a Z182 emulator probe to
grab on to the Z182 package leads on the target system.
Mode 3 RESERVED (for test purposes only)
This mode is reserved for test purpose only, do not use.
Notes:
Z182 has two branches of reset. /RESET controls the Z182
overall configuration, RAM and ROM boundaries, plus the
ESCC, Port and the 16550 MIMIC interface. In Normal
Mode, a "one shot" circuit samples the input of the /RESET
pin to assert the internal reset to its proper duration. In
Adapter Mode, this "one shot" circuit is bypassed. Note
also that the Z180’s crystal oscillator is disabled in Mode
1 and Mode 2.
In Mode 1 the emulator must provide /MREQ on the
(/MREQ,/MRD) Z80182/Z8L182 pin (not /MRD); and A18
(not T
The following signals are High-Z during SLEEP and HALT:
A0-A19 (A18 if selected) always High-Z in power down.
D0-D7 always High-Z in power down modes.
The MIMIC logic of the 182 is disabled during power down
modes of the Z180.
OUT
/IOCS when so selected in the Interrupt
Edge/Pin MUX Register.
/RD and /WR.
) on the A18/T
OUT
pin.
Z
ILOG
I
NTELLIGENT
Z80182/Z8L182
P
ERIPHERAL
3-79