Z8L18220ASC Zilog, Z8L18220ASC Datasheet - Page 45
![IC 20MHZ STATIC MIMIC 100-LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
Z8L18220ASC
Manufacturer Part Number
Z8L18220ASC
Description
IC 20MHZ STATIC MIMIC 100-LQFP
Manufacturer
Zilog
Datasheet
1.Z8018233FSG.pdf
(109 pages)
Specifications of Z8L18220ASC
Processor Type
Z180
Features
Smart Peripheral Controller
Speed
20MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
ADDITIONAL FEATURES ON THE Z182 MPU
The following is a detailed description of the enhancements
to the Z8S180 from the standard Z80180 in the areas of
STANDBY, IDLE, and STANDBY-QUICK RECOVERY
modes.
Add-On Features
There are five different power-down modes. SLEEP and
SYSTEM STOP are inherited from the Z80180. In SLEEP
mode, the CPU is in a stopped state while the on-chip
Notes:
†
minimum recovery time can be achieved if INTERRUPT is used as the
Recovery Source.
DS971820600
Power-Down
Modes
SLEEP
I/O STOP
SYSTEM STOP
IDLE
STANDBY
STANDBY Mode
The Z8S180 has been designed to save power. Two low-
power programmable power-down modes have been
added; STANDBY mode and IDLE mode. The
STANDBY/IDLE mode is selected by multiplexing D6 and
D3 of the CPU Control Register (CCR, I/O Address = 1FH).
To enter STANDBY mode:
1. Set D6 and D3 to 1 and 0, respectively.
2. Set the I/O STOP bit (D5 of ICR,
3. Execute the SLEEP instruction.
When the part is in STANDBY mode, it behaves similar to
the SYSTEM STOP mode which currently exists on the
Z80180, except that the STANDBY mode stops the external
oscillator, internal clocks and reduces power consumption
to typically 50 A..
Since the clock oscillator has been stopped, a restart of
the oscillator requires a period of time for stabilization. An
Zilog
IDLE and STANDBY modes are only offered in Z8S180. Note that the
I/O Address = 3FH) to 1.
†
†
CPU
Core
Stop
Running
Stop
Stop
Stop
On-Chip
I/O
Running
Stop
Stop
Stop
Stop
OSC.
Running
Running
Running
Running
Stop
Table 10. Power Down Modes
P R E L I M I N A R Y
PS009801-0301
CLKOUT
Running
Running
Running
Stop
Stop
18-bit counter has been added in the Z8S180 to allow for
oscillator stabilization. When the part receives an external
IRQ or BUSREQ during STANDBY mode, the oscillator is
restarted and the timer counts down 2
acknowledgment is sent to the interrupt source.
The recovery source needs to remain asserted for duration
of the 2
The following is a description of how the part exits STANDBY
for different interrupts and modes of operation.
STANDBY Mode Exit with /RESET
The /RESET input needs to be asserted for a duration long
enough for the crystal oscillator to stabilize and then exit
from the STANDBY mode. When /RESET is de-asserted, it
goes through the normal reset timing to start instruction
execution at address (logical and physical) 0000H.
The clocking is resumed within the Z8S180 and at the
system clock output after /RESET is asserted when the
crystal oscillator is restarted, but not yet stabilized.
I/Os are still operating. In I/O STOP mode, the on-chip I/Os
are in a stopped state while leaving the CPU running. In
SYSTEM STOP mode, both the CPU and the on-chip I/Os
are in the stopped state to reduce the current consumption.
The Z8S180 has added two additional power-down modes,
STANDBY and IDLE, to reduce the current consumption
even further. The differences among these power-down
modes are summarized in Table 10.
Recovery
Source
RESET, Interrupts
By Programming
RESET, Interrupts
RESET, Interrupts, BUSREQ
RESET, Interrupts, BUSREQ
17
count, otherwise standby will be resumed.
Recovery Time
(Minimum)
1.5 Clock
-
1.5 Clock
8 +1.5 Clock
2
2
17
6
+1.5 Clock (Quick Recovery)
+1.5 Clock (Normal Recovery)
Z
ILOG
I
NTELLIGENT
17
counts before
Z80182/Z8L182
P
ERIPHERAL
3-45