EZ80L92AZ050EG Zilog, EZ80L92AZ050EG Datasheet - Page 26
EZ80L92AZ050EG
Manufacturer Part Number
EZ80L92AZ050EG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050EG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3877
EZ80L92AZ050EG
EZ80L92AZ050EG
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
EZ80L92AZ050EG
Manufacturer:
ZILOG
Quantity:
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Manufacturer:
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Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
PS013014-0107
Pin No
94
95
96
97
98
99
100
PB6
PB7
PHI
Symbol
MISO
MOSI
V
V
SDA
SCL
DD
SS
Function
GPIO Port B
Master In
Slave Out
GPIO Port B
Master Out
Slave In
Power Supply
Ground
I
I
Clock
System Clock
2
2
C Serial Data Bidirectional
C Serial
Signal Direction
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Output
This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or
open-source output.
The MISO line is configured as an input
when the eZ80L92 MCU is an SPI master
device and as an output when eZ80L92
MCU is an SPI slave device. This signal is
multiplexed with PB6.
This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or
open-source output.
The MOSI line is configured as an output
when the eZ80L92 MCU is an SPI master
device and as an input when the eZ80L92
MCU is an SPI slave device. This signal is
multiplexed with PB7.
Power Supply.
Ground.
This pin carries the I
This pin is used to receive and transmit
the I
This pin is an output driven by the internal
system clock.
Description
2
C clock.
Product Specification
2
C data signal.
Architectural Overview
20
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