EZ80L92AZ050EG Zilog, EZ80L92AZ050EG Datasheet - Page 134
EZ80L92AZ050EG
Manufacturer Part Number
EZ80L92AZ050EG
Description
IC WEBSERVER 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050EG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80L92x
Core
eZ80
Data Bus Width
8 bit
Program Memory Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80L920210ZCO
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3877
EZ80L92AZ050EG
EZ80L92AZ050EG
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Serial Peripheral Interface
PS013014-0107
The Serial Peripheral Interface (SPI) is a synchronous interface allowing several SPI-type
devices to be interconnected. The SPI is a full-duplex, synchronous, and character-
oriented communication channel that employs a four-wire interface. The SPI block con-
sists of a transmitter, receiver, baud rate generator, and control unit. During an SPI trans-
fer, data is sent and received simultaneously by both the master and the slave SPI devices.
In a serial peripheral interface, separate signals are required for data and clock. The SPI
may be configured as either a master or a slave. The connection of two SPI devices (one
master and one slave) and the direction of data transfer is demonstrated in
Figure
DATAIN
ENABLE
DATAIN
CLKIN
28.
SS
MISO
SS
MOSI
SCK
Bit 0
Bit 0
Baud Rate
Generator
8-Bit Shift Register
8-Bit Shift Register
Figure 27. SPI Master Device
MASTER
Figure 28. SPI Slave Device
SLAVE
Bit 7
Bit 7
SCK
MISO
DATAOUT
CLKOUT
DATAOUT
Product Specification
Serial Peripheral Interface
eZ80L92 MCU
Figure 27
and
128
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