Z8018010FEG Zilog, Z8018010FEG Datasheet - Page 14

• Manufacturer Part Number: Z8018010FEG
• Description: IC Z180 MPU 80QFP
• Manufacturer: Zilog

Specifications of Z8018010FEG

• Processor Type: Z180
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-QFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Table 2. Pin Status During RESET BUSACK and SLEEP(continued) (continued)
PS014004-1106
Pin Number and
Package Type
QFP
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PLCC
60
61
62
63
64
65
66
67
68
1
2
3
4
5
6
7
8
Pin Descriptions
A
The address bus provides the address for memory data bus exchanges, up to 1 MB, and I/O
data bus exchanges, up to 64 KB. The address bus enters a high-impedance state during reset
and external bus acknowledge cycles. Address line
programmable reload timer (PRT) channel 1 (
address line
0–A19. Address Bus (output, active High, 3-state)
DIP
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
Default
Function
HALT
NC
NC
RFSH
IORQ
MREQ
E
M1
WR
RD
PHI
V
V
XTAL
NC
EXTAL
WAIT
BUSACK
BUSREQ
RESET
A19
SS
SS
is not available in DIP versions of the Z80180.
Secondary
Function
Pin Status
RESET BUSACK
1
1
1
1
0
1
1
1
OUT
GND
GND
OUT
IN
IN
1
IN
IN
T
OUT
IN
1
OUT
3T
3T
OUT
1
3T
3T
OUT
GND
GND
OUT
IN
OUT
IN
IN
, selected as address output on reset) and
A18
—A
is multiplexed with the output of
0
–A
SLEEP
0
OUT
1
1
OUT
1
1
1
OUT
GND
GND
OUT
IN
IN
OUT
IN
IN
19
form a 20-bit address bus.
Microprocessor Unit
Overview
Z80180
8