Z84C2008PEG Zilog, Z84C2008PEG Datasheet - Page 54
![IC 8MHZ Z80 CMOS PIO 40-DIP](/photos/6/57/65796/269-40-dip_sml.jpg)
Z84C2008PEG
Manufacturer Part Number
Z84C2008PEG
Description
IC 8MHZ Z80 CMOS PIO 40-DIP
Manufacturer
Zilog
Series
Z80r
Specifications of Z84C2008PEG
Processor Type
Z80
Features
Low Power CMOS
Speed
8MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z84C2xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z84C2008PEG
Manufacturer:
Zilog
Quantity:
20
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34
UM008005-0205
Z80 CPU
User’s Manual
Examples of Specific Z80 Instructions
After the execution of an instruction that sets a flag, that flag can be used to
control a conditional jump or return instruction. These instructions provide
logical control following the manipulation of single bit, 8-bit byte, or 18-bit
data quantities.
A full set of logical operations, including
CPL
tions between the accumulator and all other 8-bit registers, memory loca-
tions, or immediate operands.
In addition, a full set of arithmetic and logical shifts in both directions are
available which operate on the contents of all 8-bit primary registers or
directly on any memory location. The carry flag can be included or set by
these shift instructions to provide both the testing of shift results and to link
register/register or register/memory shift operations.
Example One:
When a 737-byte data string in memory location DATA must be moved to
location BUFFER, the operation is programmed as follows:
Eleven bytes are required for this operation and each byte of data is moved
in 21 clock cycles.
LD
LD
LD
LDIR
(
NOR
HL, DATA
DE, BUFFER;START ADDRESS OF TARGET BUFFER
BC, 737
), and
NEG
(two’s complement) are available for Boolean opera-
;START ADDRESS OF DATA STRING
;LENGTH OF DATA STRING
;MOVE STRING - TRANSFER MEMORY POINTED
;TO BY HL INTO MEMORY LOCATION POINTED
;TO BY DE INCREMENT HL AND DE,
;DECREMENT BC PROCESS UNTIL BC = 0.
Hardware and Software Implementation Examples
AND
,
OR
,
XOR
(exclusive-
OR
),
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