MPC8360EVVAJDGA Freescale Semiconductor, MPC8360EVVAJDGA Datasheet - Page 91

• Manufacturer Part Number: MPC8360EVVAJDGA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8360EVVAJDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8360E-RDK
• Maximum Clock Frequency: 533 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 740
• Rohs Compliant: Yes
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.2
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
in
Freescale Semiconductor
1
2
CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be pulled down (low) in
agent mode.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
Table 73
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
CFG_CLKIN_DIV
at Reset
High
High
High
High
High
High
High
High
High
High
High
Core PLL Configuration
should be considered reserved.
1
Table 73
0–1
nn
00
01
10
11
00
01
10
RCWL[COREPLL]
SPMF
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
Table 72. CSB Frequency Options (continued)
shows the encodings for RCWL[COREPLL]. COREPLL values not listed
0000
0001
0001
0001
0001
0001
0001
0001
2–5
Table 73. e300 Core PLL Configuration
Input Clock Ratio
6
n
0
0
0
0
1
1
1
csb_clk :
10:1
11:1
12:1
13:1
14:1
15:1
16:1
6:1
7:1
8:1
9:1
clocks core directly)
core_clk : csb_clk
(PLL off, csb_clk
PLL bypassed
Ratio
1.5:1
1.5:1
1.5:1
2
1:1
1:1
1:1
1:1
16.67
clocks core directly)
Input Clock Frequency (MHz)
(PLL off, csb_clk
PLL bypassed
csb_clk Frequency (MHz)
VCO divider
25
÷
÷
÷
÷
÷
÷
÷
2
4
8
8
2
4
8
33.33
200
233
2
66.67
Clocking
91