MPC8360EVVAJDGA Freescale Semiconductor, MPC8360EVVAJDGA Datasheet - Page 49

• Manufacturer Part Number: MPC8360EVVAJDGA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8360EVVAJDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8360E-RDK
• Maximum Clock Frequency: 533 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 740
• Rohs Compliant: Yes
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.2
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device.
Table 43
Freescale Semiconductor
At recommended operating conditions (see
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock duty cycle
JTAG external clock rise and fall times
TRST assert time
Input setup times:
Input hold times:
Valid times:
Output hold times:
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications herein follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
for inputs and t
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. Also, t
data input signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
provides the JTAG AC timing specifications as defined in
JTAG AC Electrical Characteristics
(first two letters of functional block)(reference)(state)(signal)(state)
Table 43. JTAG AC Timing Specifications (Independent of CLKIN)
Parameter
Table
2).
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
TCLK
TCLK
.
JTG
.
TMS, TDI
TMS, TDI
clock reference (K) going to the high (H) state. Note that, in general,
TDO
TDO
TDO
JTDXKH
t
t
JTGR
JTKHKL
Symbol
t
t
t
t
t
t
t
t
t
t
for outputs. For example, t
JTDXKH
JTDVKH
JTKLOV
JTKLDX
JTKLOZ
symbolizes JTAG timing (JT) with respect to the time
JTKLDV
JTKLOX
JTKLDZ
JTIVKH
JTIXKH
t
(first two letters of functional block)(signal)(state) (reference)(state)
f
t
TRST
JTG
JTG
& t
/t
JTGF
JTG
2
TCLK
Figure 30
to the midpoint of the signal in question.
Min
30
45
25
10
10
0
0
4
4
2
2
2
2
2
2
through
JTDVKH
Max
33.3
55
11
11
19
—
—
—
—
—
—
—
—
1
2
9
Figure
symbolizes JTAG
Figure
JTG
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
%
33.
clock
22).
Notes
5, 6
—
—
—
—
JTAG
3
4
4
5
5
6
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