A80960HD80SL2GK Intel, A80960HD80SL2GK Datasheet - Page 12

• Manufacturer Part Number: A80960HD80SL2GK
• Description: IC I960HD 3.3V 80MHZ 168CPGA
• Manufacturer: Intel

Specifications of A80960HD80SL2GK

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: HD suffix, 32-Bit, 40MHz Bus
• Speed: 80MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 168-CPGA
• Other names: 815177

80960HA/HD/HT
2.2.6
2.2.7
12
Table 2.
Table 3.
Dual Programmable Timers
The processor provides two independent 32-bit timers, with four programmable clock rates. The
user configures the timers through the Timer Unit registers. These registers are memory-mapped
within the 80960Hx, addressable on 32-bit boundaries. The timers have a single-shot mode and
auto-reload capabilities for continuous operation. Each timer has an independent interrupt request
to the processor’s interrupt controller.
Processor Self Test
When a system error is detected, the FAIL pin is asserted, a fail code message is driven onto the
address bus, and the processor stops execution at the point of failure. The only way to resume
normal operation is to perform a RESET operation. Because System Error generation may occur
sometime after the bus confidence test and even after initialization during normal processor
operation, the FAIL pin is HIGH (logic “1”) before the detection of a System Error.
The processor uses only one read bus-transaction to signal the fail code message; the address of the
bus transaction is the fail code itself. The fail code is of the form: 0xfeffffnn; bits 6 to 0 contain a
mask recording the possible failures. Bit 7, when set to 1, indicates that the mask contains failures
from the internal Built-In Self-Test (BIST); when 0, the mask indicates other failures.
Ignore reserved bits 0 and 1. Also ignore bits 5 and 6 when bit 7 is clear (=0).
The mask is shown in
Fail Codes For BIST (bit 7 = 1)
Remaining Fail Codes (bit 7 = 0)
Bit
Bit
6
5
4
3
2
1
0
6
5
4
3
2
1
0
On-chip Data-RAM failure detected by BIST.
Internal Microcode ROM failure detected by BIST.
Instruction cache failure detected by BIST.
Data cache failure detected by BIST.
Local-register cache or processor core failure detected by BIST.
Reserved. Always zero.
Reserved. Always zero.
Reserved. Always one.
Reserved. Always one.
A data structure within the IMI is not aligned to a word boundary.
A System Error during normal operation has occurred.
The Bus Confidence test has failed.
Reserved. Always zero.
Reserved. Always zero.
Table 2
and
Table
3.
When Set
When Set
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