MPC8272VRTIEA Freescale Semiconductor, MPC8272VRTIEA Datasheet - Page 58

IC MPU POWERQUICC II 516-PBGA

MPC8272VRTIEA

Manufacturer Part Number
MPC8272VRTIEA
Description
IC MPU POWERQUICC II 516-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8272VRTIEA

Processor Type
MPC82xx PowerQUICC II 32-bit
Speed
400MHz
Voltage
1.5V
Mounting Type
Surface Mount
Package / Case
516-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Document Revision History
58
Revision
1.1
1.0
01/2005
12/2004
Date
• Modification for correct display of assertion level (“overbar”) for some signals
• Section 1.1: Added 8:1 ratio to Internal CPM/bus clock multiplier values
• Section 2: removed voltage tracking note
• Section 4.6: Updated description of layout practices
• Section 6: Added sentence providing derating factor
• Section 6.1: added Note: Rise/Fall Time on CPM Input Pins
• Section 6.2: added spread sprectrum clocking note
• Section 6.2: added CLKIN jitter note
• Section 7: unit of ns added to Tval notes
• Section 7: Updated all notes to reflect updated CPU Fmin of 150 MHz commercial temp
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 2
Table
Table
Table
pullup removed.
Table
Table
Table
reflect configurable impedance
Table
sp42, sp43, sp42a
Table
Table
Table
devices, 175 MHz extended temp; CPM Fmin of 120 MHz.
Section 7, “Clock Configuration
of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz.
Table
Table
Table
Table 22. Document Revision History (continued)
3: Note 2 updated regarding VDD/VCCSYN relationship to VDDH during power-on reset
4: Updated VDD and VCCSYN to 1.425 V - 1.575 V
5: Note 2 updated to reflect VIH=2.5 for TCK, TRST, PORESET; request for external
5: Note 3 added regarding IIC compatibility
7: Updated nominal and maximum power dissipation values
8: updated PCI impedance to 27Ω, updated 60x and MEMC values and added note to
9: updated values for following specs: sp36b, sp37a, sp38a, sp39a, sp38b, sp40, sp41,
10: updated values for following specs: sp16a, sp16b, sp18a, sp18b, sp20, sp21, sp22
11: combined specs sp11 and sp11a
12: sp30 Data Bus minimum delay values changed to 0.8
20: correct superscript of footnote number after pin AD22
20: remove DONE3 from PC12
20: signals referring to TDMs C2 and D2 removed
Modes”: Updated all table footnotes reflect updated CPU Fmin
Substantive Changes
Freescale Semiconductor

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