XS1-L01A-LQ64-C5-THS XMOS, XS1-L01A-LQ64-C5-THS Datasheet - Page 9

• Manufacturer Part Number: XS1-L01A-LQ64-C5-THS
• Description: IC MPU 32BIT SINGLE CORE 64LQFP
• Manufacturer: XMOS

Specifications of XS1-L01A-LQ64-C5-THS

• Processor Type: XCore 32-Bit
• Speed: 500MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP Exposed Pad, 64-eLQFP, 64-HLQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 880-1022

XS1-L1 64LQFP Datasheet (2.1)
The XS1-L1 device contains a standard 5 pin JTAG interface, which allows the following
The JTAG interface on the XS1-L1 consists of the following signals:
The TRST_N pin must be driven low for at least 100ns after the power supplies are
The boundary scan TAP is a standard 1149.1 compliant TAP and can be used for
XCore, Switch and OTP for such actions as loading code and debugging. Both TAPs
which optionally add in additional TAPs into the JTAG chain for each of the Switch,
XCore and OTP. The XCore TAP allows register read/write commands to be made for
A diagram of the JTAG chain structure is shown below:
3.4 JTAG Operation
functionality:
stable to reset the JTAG circuitry. If JTAG debug is not required, the TRST_N pin can
be tied low with a 1k resistor to hold the JTAG port in reset.
Each XS1-L device contains multiple TAP controllers, each enabling different func-
tionality. Directly after reset, two TAP controllers are present in the JTAG chain - the
boundary scan TAP (BS TAP) and the chip TAP (CHIP TAP).
boundary scan of the I/O pins of the device. The chip TAP allows access into the
have an instruction register length of 4. From reset, the chip TAP is in BYPASS so
simply presents an extra 1-bit into the scan chain when shifting data.
If access to the XCore/Switch/OTP is required, the ChipTAP sets internal multiplexers
program loading/debug.
Signal
TCK
TMS
TRST_N
TDI
TDO
Boundary scan testing for verifying printed circuit board connectivity.
In-circuit source level debugging of the XCore.
Programming of the One Time Programmable (OTP) ROM.
Pin ID
29
27
26
30
31
I/O
I, PU, ST
I, PU, ST
I, PU, ST
I, PU, ST
OT, PD
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Description
Test clock
Test mode select
Test reset (active low)
Test data in
Test data out
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