MPC8250AVVPIBC Freescale Semiconductor, MPC8250AVVPIBC Datasheet - Page 15

• Manufacturer Part Number: MPC8250AVVPIBC
• Description: IC MPU POWERQUICC II 480-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8250AVVPIBC

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 300MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 480-TBGA
• Processor Series: MPC8xxx
• Core: 603e
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 300 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC82XX
• Device Core: PowerQUICC II
• Device Core Size: 32b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 2.2V
• Operating Supply Voltage (min): 1.9V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 480
• Package Type: TBGA
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• For Use With: CWH-PPC-8248N-VE - KIT EVAL SYSTEM QUICCSTART 8248
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 6
Figure 7
Freescale Semiconductor
shows the SCC/SMC/SPI/I
shows TDM input and output signals.
SCC/SMC/SPI/I2C output signals
SCC/SMC/SPI/I2C input signals
(See note.)
(See note.)
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
TDM output signals
Note: There are four possible timing conditions for SCC and SPI:
TDM input signals
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Serial CLKin
Figure 6. SCC/SMC/SPI/I
BRG_OUT
MPC8250 Hardware Specifications, Rev. 2
2
C internal clock.
Figure 7. TDM Signal Diagram
sp18a
sp20
2
C Internal Clock Diagram
sp40/sp41
sp21
sp19a
sp38a/sp39a
Electrical and Thermal Characteristics
15