MPC857TVR100B Freescale Semiconductor, MPC857TVR100B Datasheet - Page 23

• Manufacturer Part Number: MPC857TVR100B
• Description: IC MPU POWERQUICC 100MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC857TVR100B

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 100MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
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2
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4
5
6
7
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9
10
11
12
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Num
B37 UPWAIT valid to CLKOUT falling edge
B38 CLKOUT falling edge to UPWAIT valid
B39 AS valid to CLKOUT rising edge
B40 A(0:31), TSIZ(0:1), RD/WR, BURST,
B41 TS valid to CLKOUT rising edge (setup
B42 CLKOUT rising edge to TS valid (hold
B43 AS negation to memory controller
values in one cycle) or the frequency of the jitter is fast (I.e., it does not stay at an extreme value for a long time) then
the maximum allowed jitter on EXTAL can be up to 2%.
The timing for BG output is relevant when the MPC862/857T/857DSL is selected to work with internal bus arbiter.
arbiter. The timing for BG input is relevant when the MPC862/857T/857DSL is selected to work with external bus
arbiter.
signal is asserted.
for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
in B37 and B38 are specified to enable the freeze of the UPM output signals as described in
specified in
Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.
If the rate of change of the frequency of EXTAL is slow (I.e. it does not jump between the minimum and maximum
The timings specified in B4 and B5 are based on full strength clock.
The timing for BR output is relevant when the MPC862/857T/857DSL is selected to work with external bus arbiter.
For part speeds above 50MHz, use 9.80ns for B11a.
The timing required for BR input is relevant when the MPC862/857T/857DSL is selected to work with internal bus
For part speeds above 50MHz, use 2ns for B17.
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input
For part speeds above 50MHz, use 2ns for B19.
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified
The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior
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(MIN = 0.00 x B1 + 7.00)
valid to CLKOUT rising edge
(MIN = 0.00 x B1 + 7.00)
time) (MIN = 0.00 x B1 + 7.00)
time) (MIN = 0.00 x B1 + 2.00)
signals negation (MAX = TBD)
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(MIN = 0.00 x B1 + 1.00)
(MIN = 0.00 x B1 + 6.00)
Figure
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
Characteristic
22.
Table 7. Bus Operation Timings (continued)
13
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
33 MHz
Max
TBD
—
—
—
—
—
—
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
40 MHz
Max
TBD
—
—
—
—
—
—
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
50 MHz
Max
TBD
—
—
—
—
—
—
Figure
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
66 MHz
19.
Bus Signal Timing
Max
TBD
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
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