Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 321

IC 33MHZ STATIC Z180 68-PLCC

Z8S18033VSG

Manufacturer Part Number
Z8S18033VSG
Description
IC 33MHZ STATIC Z180 68-PLCC
Manufacturer
Zilog
Series
Z8018xr
Datasheets

Specifications of Z8S18033VSG

Processor Type
Z180
Features
Enhanced Z180
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Core Size
8bit
Cpu Speed
33MHz
Digital Ic Case Style
PLCC
No. Of Pins
68
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z8S180X
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
33 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 3.3 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8S18000ZEM
Minimum Operating Temperature
0 C
Base Number
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4307
Q2431383
Z8S18033VSG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8S18033VSG
Manufacturer:
Zilog
Quantity:
40
Part Number:
Z8S18033VSG
Manufacturer:
ZILOG
Quantity:
6 252
Part Number:
Z8S18033VSG
Manufacturer:
Zilog
Quantity:
10 000
A
AC characteristics
Address generation, physical
Address map
Addressing
Architecture
ASCI
Asynchronous serial communications interface
(ASCI)
I/O
I/O address translation
Logical examples
Logical memory organization
Logical space configuration
Physical address transition
Extended
I/O
Indexed
Indirect
Baud rate selection
Block diagram
Clock diagram
Control register A0
Control register A1
Control register B
Functions
Interrupt request circuit diagram
Register descriptions
Status register 0
Status register 1
14
44
184
181
182
12
182
116
197
117
141
120
123
55
131
142
125
128
117
57
64
56
59
58
140
B
Baud rate selection
Block diagram
Bus state controller
C
Central processing unit (CPU)
Circuit diagram, ASCI interrupt request
Clock generator
Clocked serial I/O (CSI/O)
CPU register configurations
CPU timing
ASCI
CSI/O
ASCI
CSI/O
DMAC
MMU
PRT
Basic instruction
BUSREQ/BUSACK Bus Exchange
HALT and Low Power modes
I/O data read/write
Internal I/O registers
MMU register description
Op Code fetch timing
Operand and data read/write
RESET
Wait state generator
157
142
117
56
150
146
Family MPU User Manual
92
25
6
13
13
23
22
27
41
18
14
UM005003-0703
176
14
60
20
Z8018x
31
140
25
305

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