Z8S18033VSG Zilog, Z8S18033VSG Datasheet - Page 110

• Manufacturer Part Number: Z8S18033VSG
• Description: IC 33MHZ STATIC Z180 68-PLCC
• Manufacturer: Zilog
• Series: Z8018xr

Specifications of Z8S18033VSG

• Processor Type: Z180
• Features: Enhanced Z180
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Core Size: 8bit
• Cpu Speed: 33MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z8S180X
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 33 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8S18000ZEM
• Minimum Operating Temperature: 0 C
• Base Number: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4307; Q2431383; Z8S18033VSG

DMA Status Register (DSTAT: 30H)
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
DE1
R/W
DE1
7
0
DMA Status Register (DSTAT)
DSTAT is used to enable and disable DMA transfer and DMA termination
interrupts. DSTAT also determines DMA transfer status, that is, completed
or in progress.
R/W
R/W
DE0
6
0
Value
DWE1
W
5
1
Description
Enable Channel 1 — When DE1 = 1 and DME = 1,
channel 1 DMA is enabled. When a DMA transfer
terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC.
When DE1 = 0 and the DMA interrupt is enabled (DIE1 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE1, DWE1 is written with
0 during the same register write access. Writing DE1 to 0
disables channel 1 DMA, but DMA is restartable. Writing
DE1 to 1 enables channel 1 DMA and automatically sets
DME (DMA Main Enable) to 1. DE1 is cleared to 0 during
RESET.
DWE0
W
4
1
DIE1
R/W
3
0
Family MPU User Manual
DIE0
R/W
2
0
UM005003-0703
1
?
?
?
Z8018x
DME
R
0
95