Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 45

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

PS014004-1106
ASCI Transmit Data Registers
Data can be written into and read from the ASCI Transmit Data Register. If data is read from
the ASCI Transmit Data Register, the ASCI data transmit operation is not affected by this
READ
ASCI Receive Shift Register 0,1 (RSR0, RSR1)—
the
(
overrun error occurs. This register is not program accessible.
ASCI Receive Data FIFO 0,1 (RDR0, RDR1)—
Data Register is a
in
(FIFO) memory. The oldest character in the FIFO (if any) can be read from the Receive Data
Register (
The ASCI receiver is well buffered.
Register addresses
respectively.
Channel 0
Mnemonics TDR0 (Address 06h)
RDR
RSR
RxA
) if it is empty. If
operation.
, it is automatically transferred to the 4 character Receive Data First-In First-Out
pin. When full, data is automatically transferred to the ASCI Receive Data Register
RDR
). The next incoming data byte can be shifted into
—-
7
READ-ONLY
Figure 28. ASCI Register Channel 0
06h
6
—
RSR
and
—-
5
07h
is not empty when the next incoming data byte is shifted in, an
—
—
4
hold the ASCI transmit data for channel 0 and channel 1,
register. When a complete incoming data byte is assembled
ASCI Transmit Channel 0
—
3
2
—
—
I/O Address =
1
This register receives data shifted in on
08h
RSR
,
09h
Microprocessor Unit
while the FIFO is full.
. The ASCI Receive
Architecture
Z80180
39