Z8018010FSG Zilog, Z8018010FSG Datasheet - Page 73
![IC 10MHZ Z180 CMOS ENH MPU 80QFP](/photos/6/76/67663/269-80-qfp_sml.jpg)
Z8018010FSG
Manufacturer Part Number
Z8018010FSG
Description
IC 10MHZ Z180 CMOS ENH MPU 80QFP
Manufacturer
Zilog
Datasheet
1.Z8018006PSG.pdf
(85 pages)
Specifications of Z8018010FSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
80-QFP
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3887
Z8018010FSG
Z8018010FSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Int/TRAP Control Register
PS014004-1106
Mnemonics ITC
Address 34
INT/TRAP Control Register (ITC, I/O Address 34h)
This register is used in handling
Level 0 and the
TRAP (bit 7)—This bit is set to
under program control by writing it with a
gram control.
UFO: Undefined Fetch Object (bit 6)—When a
a
TRAP
Program Counter (
interpreted as the stacked
READ-ONLY
ITE2, 1, 0: Interrupt Enable 2, 1, 0 (bits 2-0)—
external interrupt inputs
from the on-chip ESCC, CTCs and bidirectional Centronics controller as well as the external
interrupt input
it. A
TRAP Interrupt
The Z80180 generates a nonmaskable (not affected by the state of
when an undefined opcode fetch occurs. This feature can be used to increase software reli-
ability, implement an extended instruction set, or both.
cycles and also if an undefined opcode is fetched during the interrupt acknowledge cycle for
INT0
UFO
RESET
when Mode 0 is used.
may occur on either the second or third byte of the opcode. A
allow the starting address of the undefined instruction to be determined. However, the
Bit
TRAP
clears
.
R/W
TRAP
INT0
7
INT1
Figure 69. Int/TRAP Control Register
PC
ITE0
. A
UFO
is reset to
6
R
and
) value to be correctly adjusted. If
1
to
INT2
in a bit enables the corresponding interrupt level while a
INT2
PC-1
1
––
5
and clears
and
0
. If
pins.
TRAP
during
1
UFO = 1
––
INT1
4
when an undefined opcode is fetched.
interrupts and to enable or disable Maskable Interrupt
, respectively.
ITE1
RESET
––
3
, the first opcode address is stacked
0
, however, it cannot be written with
and
.
ITE2
R/W
2
ITE2
ITE2
TRAP
ITE1
R/W
ITE0
to
TRAP
1
UFO = 0
0
.
and
enables and disables interrupts
interrupt occurs, the contents of
R/W
ITE0
may occur during opcode fetch
0
ITE1
, the first opcode must be
IEF1
enable and disable the
Microprocessor Unit
UFO
)
TRAP
TRAP
allows the stacked
PC-2
interrupt
can be reset
1
Architecture
under pro-
0
.
disables
Z80180
UFO
is
67