Z8018010FSG Zilog, Z8018010FSG Datasheet - Page 70
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Z8018010FSG
Manufacturer Part Number
Z8018010FSG
Description
IC 10MHZ Z180 CMOS ENH MPU 80QFP
Manufacturer
Zilog
Datasheet
1.Z8018006PSG.pdf
(85 pages)
Specifications of Z8018010FSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
80-QFP
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3887
Z8018010FSG
Z8018010FSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
DMA Mode Register (DMODE: I/O Address = 31h)
PS014004-1106
Bit
Mnemonic DMODE
Address 31h
DM1, DM0: Destination Mode Channel 0 (bits 5,4)—Specifies whether the
destination for channel 0 transfers is memory or I/O, and whether the address must be incre-
mented or decremented for each byte transferred.
RESET
Table 16. Channel 0 Destination
SM1, SM0: Source Mode Channel 0 (bits 3, 2)—Specifies whether the source for
channel 0 transfers is memory or I/O, and whether the address must be incremented or
decremented for each byte transferred (see
Table 17. Channel 0 Source
Table 18
I/O to/from I/O transfers are not implemented, 12 combinations are available.
DM1
0
0
1
1
SM1
0
0
1
1
7
Figure 66. DMA Mode Register (DMODE: I/O Address = 31h)
(see
DM0
0
1
0
1
SM0
0
1
0
1
lists all DMA transfer mode combinations of
6
Table
Memory I/O
Memory
Memory
Memory
I/O
Memory I/O
Memory
Memory
Memory
I/O
DM1
R/W
16).
5
DM0
R/W
4
Memory Increment/Decrement
+1
–1
fixed
fixed
Memory Increment/Decrement
+1
–1
fixed
fixed
SM1
R/W
3
SM0
R/W
Table
2
17).
DM1
MMOD
R/W
1
DM0
and
DM0
,
DM1
0
are cleared to
,
SM0
Microprocessor Unit
, and
SM1
0
Architecture
during
. Because
Z80180
64