Z85C3008PSG Zilog, Z85C3008PSG Datasheet - Page 22
![IC 8MHZ Z8500 CMOS SCC 40-DIP](/photos/6/57/65796/269-40-dip_sml.jpg)
Z85C3008PSG
Manufacturer Part Number
Z85C3008PSG
Description
IC 8MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3008PSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
8MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
Through Hole
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3930
Q2456016A
Z85C3008PSG
Q2456016A
Z85C3008PSG
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PS011705-0608
Each interrupt type is enabled under program control with Channel A having higher
priority than Channel B, and with Receiver, Transmit, and External/Status interrupts
prioritized in that order within each channel.
When enabled, the receiver interrupts the CPU in one of three ways:
Interrupt on First Character or Special Condition and Interrupt on Special Condition Only
are typically used with the Block Transfer mode. A special Receive Condition is one of the
following. receiver overrun, framing error in Asynchronous mode, end-of-frame in SDLC
mode and, optionally, a parity error. The Special Receive Condition interrupt is different
from an ordinary receive character available interrupt only by the status placed in the vec-
tor during the Interrupt Acknowledge cycle. In Interrupt on First Receive Character, an
interrupt occurs from Special Receive Conditions anytime after the first receive character
interrupt.
The main function of the External/Status interrupt is to monitor the signal transitions of
the CTS, DCD, and SYNC pins, however, an External/Status interrupt is also caused by a
Transmit Underrun condition; a zero count in the Baud Rate Generator; by the detection of
a Break (Asynchronous mode), Abort (SDLC mode) or EOP (SDLC Loop mode)
sequence in the data stream. The interrupt caused by the Abort or EOP has a special fea-
ture allowing the SCC to interrupt when the Abort or EOP sequence is detected or termi-
nated. This feature facilitates the proper termination of the current message, correct
initialization of the next message, and the accurate timing of the Abort condition in exter-
nal logic in SDLC mode. In SDLC Loop mode, this feature allows secondary stations to
recognize the primary station regaining control of the loop during a poll sequence.
Software Interrupt Acknowledge
On the CMOS version of the SCC, the SCC interrupt acknowledge cycle can be initiated
through software. If Write Register 9 (WR9) bit D5 is set, Read Register 2 (RR2) results in
an interrupt acknowledge cycle to be executed internally. Like a hardware INTACK cycle,
a software acknowledge causes the INT pin to return High, the IEO pin to go low and set
the IUS latch for the highest priority interrupt pending.
Similar to using the hardware INTACK signal, a software acknowledge cycle requires that
a Reset Highest IUS command be issued in the interrupt service routine. Whenever an
interrupt acknowledge cycle is used, hardware or software, a reset highest IUS command
is required. If RR2 is read from channel A, the unmodified vector is returned. If RR2 is
read from channel B, then the vector is modified to indicate the source of the interrupt.
The Vector Includes Status (VIS) and No Vector (NV) bits in WR9 are ignored when bit
05 is set to 1.
•
•
•
•
External/Status
Interrupt on First Receive Character or Special Receive Condition
Interrupt on All Receive Characters or Special Receive Conditions
Interrupt on Special Receive Conditions Only
CMOS SCC Serial Communications Controller
Product Specification
Functional Description
18