20-668-0024 Rabbit Semiconductor, 20-668-0024 Datasheet - Page 345

• Manufacturer Part Number: 20-668-0024
• Description: IC CPU RABBIT4000 128-LQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 20-668-0024

• Processor Type: Rabbit 4000 8-bit
• Speed: 60MHz
• Voltage: 2.5V, 2.7V, 3V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 20-668-0022; 316-1078

B.2 Bugs
The following bugs have been identified in the Rabbit 4000 design, and are present in all
devices currently available.
1. Primary/secondary watchdog timer interaction — if the secondary watchdog timer
2. Stack protection/DMA interaction — when stack protection is enabled and a DMA
3. DMA/HDLC/Ethernet interaction — a specific bug can manifest itself when the
Appendix B Rabbit 4000 ESD Design Guidelines and Bug Workarounds
is enabled when a primary watchdog timeout occurs (resetting the processor), the sec-
ondary watchdog timer is still enabled when the device comes out of reset, which is not
the documented behavior (the secondary watchdog should be disabled on reset).
The BIOS provided by Rabbit Semiconductor in Dynamic C avoids this bug by disabling
the secondary watchdog on startup or reset by writing 0x5F to WDTCR. The secondary
watchdog timer is then enabled if needed with the
macro.
transfer is occurring, the stack protection interrupt will occur if the lower 16 bits of a
DMA transfer’s physical write address match the 16 bits of the stack protection’s logical
address limits.
following conditions are present.
When all these conditions occur, the DMA will overwrite the next-to-last byte in the
transmit FIFO, and that particular byte will never be transmitted.
There are several ways to avoid this bug.
The Ethernet driver provided by Rabbit Semiconductor in Dynamic C is written so that
this bug never occurs.
• The HDLC or Ethernet peripherals are being fed bytes for transmit via DMA.
• The current DMA buffer has been marked with “special treatment for last byte.”
• The buffer has not been marked as “final buffer.”
• The DMA fills the transmit FIFO with the next-to-last byte of the buffer and then either switches to
• The DMA then returns to the channel before the transmitter has had a chance to transmit a single
• Always mark the buffer that contains the end-of-frame byte as the final buffer, and restart the DMA
• Make sure that the DMA will not return to this channel before the transmitter has sent one byte
• Place the end-of-frame byte in a separate DMA buffer.
another channel or releases the bus.
byte, freeing space in the transmit FIFO.
once that buffer has been transmitted.
from the transmit FIFO.
#define USE_SECONDARY_WD
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