20-668-0024 Rabbit Semiconductor, 20-668-0024 Datasheet - Page 195

• Manufacturer Part Number: 20-668-0024
• Description: IC CPU RABBIT4000 128-LQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 20-668-0024

• Processor Type: Rabbit 4000 8-bit
• Speed: 60MHz
• Voltage: 2.5V, 2.7V, 3V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 20-668-0022; 316-1078

19.3.6 DMA with Peripherals
When the DMA is directed towards an internal I/O address, the DMA transfer request
signals will be connected as appropriate for that peripheral. For example, when a DMA
transfer is performed to Serial Port D’s data register, the transfer request will be enabled
whenever the serial port transmit buffer is empty, and will be disabled whenever it is not.
19.3.6.1 DMA with HDLC Serial Ports
The HDLC serial ports receive special handing by the DMA. When the DMA destination
is Serial Port E’s or Serial Port F’s data register (SxDR), the final byte of the transfer will
be written to the appropriate last data register (SxLDR) as required to complete an HDLC
packet and append the CRC value. In addition, the value in the appropriate status register
(SxSR) will be written to the status byte in the buffer descriptor pointed to by the initial
address registers (not necessarily the buffer descriptor that is currently being used). These
features allow an application to automatically send and receive packets via DMA, only
requiring direct handling of a packet when an error occurs.
19.3.6.2 DMA with Ethernet
The Ethernet network peripheral also receives special handing by the DMA. When the
DMA destination is the network data register (NADR), the final byte of the transfer will
be written to the last data register (NALDR) as required to complete an Ethernet packet
and append the CRC value. In addition, the value in the network status register (NASR)
will be written to the status byte in the buffer descriptor pointed to by the initial address
registers (not necessarily the buffer descriptor that is currently being used). These features
allow the processor to only handle interrupts when an error occurs.
19.3.6.3 DMA with PWM and Timer C
The PWM and Timer C peripherals have special support for DMA; the block access and
pointer registers in each of these peripherals provide a means for the DMA to update the
settings of these peripherals at some desired rate. This allows complex PWM waveforms
to be generated by using the DMA timed request to update the PWM duty cycles at regular
intervals.
19.3.7 DMA Bug Workarounds (Appendix B.2)
19.3.7.1 DMA/HDLC/Ethernet Interaction
A specific bug can manifest itself when the following conditions are present.
Chapter 19 DMA Channels
• The HDLC or Ethernet peripherals are being fed bytes for transmit via DMA.
• The current DMA buffer has been marked with “special treatment for last byte.”
• The buffer has not been marked as “final buffer.”
• The DMA fills the transmit FIFO with the next-to-last byte of the buffer and then either switches to
• The DMA then returns to the channel before the transmitter has had a chance to transmit a single
another channel or releases the bus.
byte, freeing space in the transmit FIFO.
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