CY7C67300-100AXE Cypress Semiconductor Corp, CY7C67300-100AXE Datasheet - Page 61

• Manufacturer Part Number: CY7C67300-100AXE
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r

Specifications of CY7C67300-100AXE

• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HPI Registers
There are five registers dedicated to HPI operation. In addition,
there is an HPI status port which can be addressed over HPI.
Each of these registers is covered in this section and are summa-
rized in
HPI Breakpoint Register [0x0140] [R]
Table 99. HPI Breakpoint Register
Register Description
The HPI Breakpoint register is a special on-chip memory location
that the external processor can access using normal HPI
memory read/write cycles. This register is read only by the CPU
but is read/write by the HPI port. The contents of this register
have the same effect as the Breakpoint register [0xC014]. This
special Breakpoint register is used by software debuggers that
interface through the HPI port instead of the serial port.
Interrupt Routing Register [0x0142] [R]
Table 100. Interrupt Routing Register
Register Description
The Interrupt Routing register allows the HPI port to take over
some or all of the SIE interrupts that usually go to the on-chip
CPU. This register is read only by the CPU but is read/write by
the HPI port. By setting the appropriate bit to ‘1’, the SIE interrupt
is routed to the HPI port to become the HPI_INTR signal and also
readable in the HPI Status register. The bits in this register select
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Table
98.
VBUS to HPI
Resume2 to
HPI Enable
Enable
15
15
R
R
0
7
0
0
7
0
-
-
Resume1 to
HPI Enable
ID to HPI
Enable
14
14
R
R
0
6
0
0
6
0
-
-
SOF/EOP2 to
HPI Enable
13
13
R
R
0
5
0
0
5
0
-
-
Reserved
SOF/EOP2 to
CPU Enable
12
12
R
R
0
4
0
1
4
0
-
-
Address...
...Address
Table 98. HPI Registers
When the program counter matches the Breakpoint Address, the
INT127 interrupt triggers. To clear this interrupt, write a zero a to
this register.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint
address.
where the interrupts are routed. The individual interrupt enable
is handled in the SIE interrupt enable register.
VBUS to HPI Enable (Bit 15)
The VBUS to HPI Enable bit routes the OTG VBUS interrupt to
the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
HPI Breakpoint Register
Interrupt Routing Register
SIE1msg Register
SIE2msg Register
HPI Mailbox Register
SOF/EOP1 to
Done2 to HPI
HPI Enable
Enable
Register Name
11
11
R
R
3
0
0
3
0
0
-
-
SOF/EOP1 to
Done1 to HPI
CPU Enable
Enable
10
10
R
R
2
0
0
2
0
1
-
-
0x0142
0x0144
0x0148
0x0140
0xC0C6
Reset1 to HPI
Reset2 to HPI
Address
Enable
Enable
R
R
1
0
9
0
1
0
9
0
-
-
CY7C67300
HPI Swap 0
HPI Swap 1
Enable
Enable
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R
R
0
0
8
0
0
0
8
0
-
R/W
R/W
-
W
W
R
R
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