CY7C53120E2-10SXIT Cypress Semiconductor Corp, CY7C53120E2-10SXIT Datasheet - Page 6

• Manufacturer Part Number: CY7C53120E2-10SXIT
• Description: IC PROCESSOR NEURON 32-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: Neuron®r

Specifications of CY7C53120E2-10SXIT

• Applications: Network Processor
• Core Processor: Pipelined
• Program Memory Type: FLASH (2 kB), ROM (10 kB)
• Controller Series: CY7C531xx
• Ram Size: 2K x 8
• Interface: Serial
• Number Of I /o: 11
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-SOIC (11.30mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-10001 Rev. *E
Programmable Hysteresis Values
(Expressed as differential peak-to-peak voltages in terms of V
Programmable Glitch Filter Values
(Receiver (end-to-end) filter values expressed as transient
pulse suppression times)
Notes
6. Hysteresis values are on the condition that the input signal swing is 200 mV greater than the programmed value.
7. Must be disabled if data rate is 1.25 Mbps or greater.
8. Receiver input, V
9. CPO and CP1 inputs each 0.60 Vp – p, 1.25 MHz sine wave 180° out of phase with each other as shown in
10. t
Hysteresis
Filter (F)
PLH
0
1
2
3
: Time from input switching states from low to high to output switching states. t
0
1
2
3
4
5
6
7
[6]
D
= V
Min.
120
240
480
0.019 V
0.040 V
0.061 V
0.081 V
0.101 V
0.121 V
0.142 V
0.162 V
V
10
CP0
hys
– V
Min.
CP1
DD
DD
DD
DD
DD
DD
DD
DD
, at least 200 mV greater than hysteresis levels. See
1500
Typ.
410
800
75
0.027 V
0.054 V
0.081 V
0.108 V
0.135 V
0.162 V
0.189 V
0.216 V
V
hys
[7]
Typ.
DD
DD
DD
DD
DD
DD
DD
DD
Max.
1350
2600
140
700
0.035 V
0.068 V
0.101 V
0.135 V
0.169 V
0.203 V
0.236 V
0.270 V
V
hys
Max.
Unit
ns
ns
ns
ns
DD
DD
DD
DD
DD
DD
DD
DD
DD
)
Receiver
(Worst case across hysteresis)
Differential Receiver (End-to-End) Absolute Symmetry
PHL
Filter (F)
: Time from input switching states from high to low to output switching states.
Filter (F)
Figure
0
0
1
2
3
V
[8]
DD
CP0
CP1
⎮
1.
Figure 1. Receiver Input Waveform
V
(End-to-End) Absolute Asymmetry
/2
CP0 – CP1
hys
Hysteresis (H)
+ 200 mV
Figure
0
⎮
≥
Max (
8. V
DD
≤ 3 ns
⎢
t
= 5.00 V ± 5%.
PLH
150
250
400
Max (
35
– t
PHL
⎢
CY7C53150
CY7C53120
t
PLH
24
⎜
)
– t
Page 6 of 14
PHL
⎜
) Unit
Unit
ns
ns
ns
ns
[9, 10]
ns
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