CY7C64113C-PVXC Cypress Semiconductor Corp, CY7C64113C-PVXC Datasheet - Page 27

• Manufacturer Part Number: CY7C64113C-PVXC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 29. USB Endpoint Interrupt Enable Register
Bit 0: EPA0 Interrupt Enable
Bit 1: EPA1 Interrupt Enable
Bit 2: EPA2 Interrupt Enable
Bit 3: EPB0 Interrupt Enable
Bit 4: EPB1 Interrupt Enable
Bit [7..5] : Reserved
During a reset, the contents the Global Interrupt Enable Register
and USB End Point Interrupt Enable Register are cleared,
effectively, disabling all interrupts
The interrupt controller contains a separate flip-flop for each
interrupt. See
the interrupt controller. When an interrupt is generated, it is first
registered as a pending interrupt. It stays pending until it is
serviced or a reset occurs. A pending interrupt only generates an
interrupt request if it is enabled by the corresponding bit in the
interrupt enable registers. The highest priority interrupt request
is serviced following the completion of the currently executing
instruction.
When servicing an interrupt, the hardware does the following
Document Number: 38-08001 Rev. *D
1. Disables all interrupts by clearing the Global Interrupt Enable
2. Clears the flip-flop of the current interrupt.
USB Endpoint
Interrupt
Enable
Bit #
Bit Name
Read/Write
Reset
Figure 6. USB Endpoint Interrupt Enable Register
bit in the CPU (the state of this bit can be read at Bit 2 of the
Processor Status and Control Register,
1= Enable Interrupt on data activity through endpoint A0;
0= Disable Interrupt on data activity through endpoint A0
1= Enable Interrupt on data activity through endpoint A1;
0= Disable Interrupt on data activity through endpoint A1
1= Enable Interrupt on data activity through endpoint A2;
0= Disable Interrupt on data activity through endpoint A2.
1= Enable Interrupt on data activity through endpoint B0;
0= Disable Interrupt on data activity through endpoint B0
1= Enable Interrupt on data activity through endpoint B1;
0= Disable Interrupt on data activity through endpoint B1
Figure 7 on page 28
Reserved
7
-
-
Reserved
for the logic block diagram of
6
-
-
Table 27 on page
Reserved
5
-
-
EPB1 Interrupt
25).
Enable
R/W
4
0
The instruction in the interrupt table is typically a JMP instruction
to the address of the Interrupt Service Routine (ISR). The user
can re-enable interrupts in the interrupt service routine by
executing an EI instruction. Interrupts can be nested to a level
limited only by the available stack space.
The Program Counter value as well as the Carry and Zero flags
(CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction generated as part of the interrupt acknowledge
process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt.
The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP
A instruction should be used to restore the accumulator value
just before the RETI instruction. The program counter CF and ZF
are restored and interrupts are enabled when the RETI
instruction is executed.
The DI and EI instructions can be used to disable and enable
interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to
re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exists the ISR. While the global interrupt enable bit is
cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and
Control Register).
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed
in
Bus Reset interrupt) has the highest priority, and the
highest-numbered interrupt (I
3. Generates an automatic CALL instruction to the ROM ad-
Table 30 on page
dress associated with the interrupt being serviced (i.e., the
Interrupt Vector, see
EPB0 Interrupt
Enable
R/W
3
0
EPA2 Interrupt
Enable
29. The lowest-numbered interrupt (USB
R/W
2
0
Interrupt
2
C interrupt) has the lowest priority.
EPA1 Interrupt
Vectors).
Enable
R/W
1
0
CY7C64013C
CY7C64113C
ADDRESS 0X21
EPA0 Interrupt
Page 27 of 53
Enable
R/W
0
0
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