CY7C64113C-PVXC Cypress Semiconductor Corp, CY7C64113C-PVXC Datasheet - Page 2

• Manufacturer Part Number: CY7C64113C-PVXC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Memory
The CY7C64013C and CY7C64113C have 8 KB of PROM.
Power on Reset, Watchdog and Free running Time
These parts include power-on reset logic, a Watchdog timer, and
a 12-bit free-running timer. The power-on reset (POR) logic
detects when power is applied to the device, resets the logic to
a known state, and begins executing instructions at PROM
address 0x0000. The Watchdog timer is used to ensure the
microcontroller recovers after a period of inactivity. The firmware
may become inactive for a variety of reasons, including errors in
the code or a hardware failure such as waiting for an interrupt
that never occurs.
I
The microcontroller can communicate with external electronics
through
accommodates a 100-kHz serial link with an external device.
There is also a Hardware Assisted Parallel Interface (HAPI)
which can be used to transfer data to an external device.
Timer
The free-running 12-bit timer clocked at 1 MHz provides two
interrupt sources, 128-µs and 1.024-ms. The timer can be used
to measure the duration of an event under firmware control by
reading the timer at the start of the event and after the event is
complete. The difference between the two readings indicates the
Document Number: 38-08001 Rev. *D
2
C and HAPI Interface
the
GPIO
pins.
An
I
2
C-compatible
interface
duration of the event in microseconds. The upper four bits of the
timer are latched into an internal register when the firmware
reads the lower eight bits. A read from the upper four bits actually
reads data from the internal register, instead of the timer. This
feature eliminates the need for firmware to try to compensate if
the upper four bits increment immediately after the lower eight
bits are read.
Interrupts
The microcontroller supports 11 maskable interrupts in the
vectored interrupt controller. Interrupt sources include the USB
Bus Reset interrupt, the 128-µs (bit 6) and 1.024-ms (bit 9)
outputs from the free-running timer, five USB endpoints, the DAC
port, the GPIO ports, and the I
interface. The timer bits cause an interrupt (if enabled) when the
bit toggles from LOW ‘0’ to HIGH ‘1.’ The USB endpoints interrupt
after the USB host has written data to the endpoint FIFO or after
the USB controller sends a packet to the USB host. The DAC
ports have an additional level of masking that allows the user to
select which DAC inputs can cause a DAC interrupt. The GPIO
ports also have a level of masking to select which GPIO inputs
can cause a GPIO interrupt. For additional flexibility, the input
transition polarity that causes an interrupt is programmable for
each pin of the DAC port. Input transition polarity can be
programmed for each GPIO port as part of the port configuration.
The interrupt polarity can be rising edge (‘0’ to ‘1’) or falling edge
(‘1’ to ‘0’).
2
C-compatible master mode
CY7C64013C
CY7C64113C
Page 2 of 53
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