CY7C65113-SC Cypress Semiconductor Corp, CY7C65113-SC Datasheet - Page 23

• Manufacturer Part Number: CY7C65113-SC
• Description: IC MCU 8K USB HUB 4 PORT 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1331

The I
either GPIO port 1 or GPIO port 2. The port selection is determined by settings in the I
11.0). Once the I
Figure 12-2), the two LSB ([1:0]) of the corresponding GPIO port is placed in Open Drain mode, regardless of the settings of the
GPIO Configuration Register. In Open Drain mode, the GPIO pin outputs LOW if the pin’s Data Register is ‘0’, and the pin is in
Hi-Z mode if the pin’s Data Register is ‘1’. The electrical characteristics of the I
GPIO ports 1 and 2. Note that the I
All control of the I
Bits [7..0] : I
The I
Table 12-1. I
Bit 7 : MSTR Mode
Document #: 38-08002 Rev. *B
I2C Data
Bit #
Bit Name
Read/Write
Reset
I
Bit #
Bit Name
Read/Write
Reset
2
C Status and Control
Bit
0
1
2
3
4
5
6
7
2
2
Contains the 8-bit data on the I
Setting this bit to 1 causes the I
transmitting the first data byte from the data register (this typically holds the target address and R/W bit). Subsequent bytes
are initiated by setting the Continue bit, as described below.
Clearing this bit (set to 0) causes the GPIO pins to operate normally.
In master mode, the I
transmit or receive state. The I
event of a loss of arbitration, this MSTR bit is cleared, the ARB Lost bit is set, and an interrupt is generated by the
C clock (SCL) is connected to bit 0 of either GPIO port 1 or GPIO port 2, and the I
C Status and Control register bits are defined in Table 12-1, with a more detailed description following.
I
Received Stop
ARB Lost/Restart Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.
Addr
ACK
Xmit Mode
Continue/Busy
MSTR Mode
2
2
C Enable
C Data
2
C Status and Control Register Bit Definitions
MSTR Mode Continue/Bu
I
2
2
Name
C-compatible functionality is enabled by setting the I
2
C Data 7
C clock (SCL) and data (SDA) lines is performed by the I
R/W
R/W
X
7
7
0
2
C-compatible block generates the clock (SCK), and drives the data line as required depending on
I
When set to ‘1’, the I
normally.
Reads 1 only in slave receive mode, when I
last transaction).
Write to 1 in master mode to perform a restart sequence (also set Continue bit).
Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.
Reads 0 otherwise. This bit should always be written as 0.
In receive mode, write 1 to generate ACK, 0 for no ACK.
In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
Write to 1 for transmit mode, 0 for receive mode.
Write 1 to indicate ready for next transaction.
Reads 1 when I
Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration.
Clearing from 1 to 0 generates Stop bit.
2
C Data 6
R/W
R/W
sy
X
6
6
0
OL
2
2
2
C-compatible block performs any required arbitration and clock synchronization. IN the
(max) is 2 mA @ V
C Bus.
C-compatible block to initiate a master mode transaction by sending a start bit and
Figure 12-2. I
Xmit Mode
I
2
2
C Data 5
C-compatible block is busy with a transaction, 0 when transaction is complete.
R/W
R/W
Figure 12-1. I
5
X
5
0
2
C-compatible function is enabled. When cleared, I
2
C Status and Control Register
OL
I
2
= 2.0V for ports 1 and 2.
C Data 4
R/W
ACK
R/W
2
C Data Register
X
4
4
0
2
C Enable bit of the I
Description
I
2
2
C Stop bit detected (unless firmware did not ACK the
C Data 3
2
Addr
R/W
R/W
C-compatible block.
X
3
3
0
2
C-compatible interface is the same as that of
Lost/Restart
2
I
C Port Configuration Register (Section
2
2
C Data 2
C SDA data is connected to bit 1 of
ARB
2
R/W
R/W
C Status and Control Register (bit 0,
X
2
2
0
I
Received
2
2
C Data 1
C GPIO pins operate
R/W
Stop
R/W
X
1
1
0
CY7C65013
CY7C65113
Address 0x29
Address 0x28
Page 23 of 51
I
I
2
2
C Enable
C Data 0
R/W
R/W
X
0
0
0