CY7C64113-PVC Cypress Semiconductor Corp, CY7C64113-PVC Datasheet - Page 41

• Manufacturer Part Number: CY7C64113-PVC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113-PVC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1328

Table 19-2. Details of Modes for Differing Traffic Conditions (see Table 19-1 for the decode legend)
Document #: 38-08001 Rev. *A
SETUP (if accepting SETUPs)
Properties of Incoming Packet
Mode Bits
See Table 19-1
See Table 19-1
See Table 19-1
Properties of Incoming Packet
Mode Bits
DISABLED
0
Nak In/Out
0
0
Ignore In/Out
0
0
Stall In/Out
0
0
CONTROL WRITE
Properties of Incoming Packet
Mode Bits
Normal Out/premature status In
1
1
1
1
NAK Out/premature status In
1
1
1
1
Status In/extra Out
0
0
0
0
CONTROL READ
Properties of Incoming Packet
Mode Bits
Normal In/premature status Out
1
1
1
1
1
1
Nak In/premature status Out
1
Normally the firmware should perform a register read at the beginning of the Endpoint ISRs to unlock and get the mode register information.
The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the
previous transaction. Note that the setup bit of the mode register is NOT locked. This means that before writing to the mode register,
firmware must first read the register to make sure that the setup bit is not set (which indicates a setup was received, while processing the
current USB request). This read will of course unlock the register. So care must be taken not to overwrite the register elsewhere.
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
token
Setup
Setup
Setup
token
x
Out
In
Out
In
Out
In
token
Out
Out
Out
In
Out
Out
Out
In
Out
Out
Out
In
token
Out
Out
Out
Out
Out
In
Out
count
<= 10
> 10
x
count
x
x
x
x
x
x
x
count
<= 10
> 10
x
x
<= 10
> 10
x
x
<= 10
> 10
x
x
count
2
2
!=2
> 10
x
x
2
buffer
data
junk
junk
buffer
UC
UC
UC
UC
UC
UC
UC
buffer
data
junk
junk
UC
UC
UC
UC
UC
UC
UC
UC
UC
buffer
UC
UC
UC
UC
UC
UC
UC
dval
valid
x
invalid
dval
x
x
x
x
x
x
x
dval
valid
x
invalid
x
valid
x
invalid
x
valid
x
invalid
x
dval
valid
valid
valid
x
invalid
x
valid
Changes made by SIE to Internal Registers and Mode Bits
DTOG
updates
updates
updates
Changes made by SIE to Internal Registers and Mode Bits
DTOG
UC
UC
UC
UC
UC
UC
UC
Changes made by SIE to Internal Registers and Mode Bits
DTOG
updates
updates
updates
UC
UC
UC
UC
UC
UC
UC
UC
UC
Changes made by SIE to Internal Registers and Mode Bits
DTOG
1
0
updates
UC
UC
UC
1
DVAL
DVAL
DVAL
1
updates
UC
DVAL
1
updates
0
UC
UC
UC
UC
UC
UC
UC
0
UC
UC
UC
UC
UC
UC
UC
UC
1
1
1
UC
UC
UC
1
COUNT
updates
updates
updates
COUNT
UC
UC
UC
UC
UC
UC
UC
COUNT
updates
updates
updates
UC
UC
UC
UC
UC
UC
UC
UC
UC
COUNT
updates
updates
updates
UC
UC
UC
updates
Setup
1
1
1
Setup
UC
UC
UC
UC
UC
UC
UC
Setup
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
Setup
UC
UC
UC
UC
UC
UC
UC
In
UC
UC
UC
In
UC
UC
1
UC
UC
UC
1
In
UC
UC
UC
1
UC
UC
UC
1
UC
UC
UC
1
In
UC
UC
UC
UC
UC
1
UC
Out
UC
UC
UC
Out
UC
1
UC
UC
UC
1
UC
Out
1
1
1
UC
1
UC
UC
UC
1
UC
UC
UC
Out
1
1
1
UC
UC
UC
1
ACK
1
UC
UC
ACK
UC
UC
UC
UC
UC
UC
UC
ACK
1
UC
UC
1
UC
UC
UC
1
UC
UC
UC
1
ACK
1
UC
UC
UC
UC
1
1
Mode Bits
0
NoChange
NoChange
Mode Bits
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
Mode Bits
1
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
0
NoChange
NoChange
NoChange
Mode Bits
NoChange
0
0
NoChange
NoChange
1
NoChange
0 1 0 ACK
0 0 1 ACK
0 1 1 Stall
0 1 1 Stall
0 1 1 Stall
1 1 0 ACK (back)
CY7C64013
CY7C64113
Response
ignore
ignore
Response
ignore
NAK
NAK
ignore
ignore
Stall
Stall
Response
ignore
ignore
TX 0
NAK
ignore
ignore
TX 0
ignore
ignore
TX 0
Response
ACK
ignore
ignore
ACK
Page 41 of 51
Intr
yes
yes
yes
Intr
no
yes
yes
no
no
yes
yes
Intr
yes
yes
yes
yes
yes
no
no
yes
yes
no
no
yes
Intr
yes
yes
yes
no
no
yes
yes