CY7C64113-PVC Cypress Semiconductor Corp, CY7C64113-PVC Datasheet - Page 29

• Manufacturer Part Number: CY7C64113-PVC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113-PVC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1328

16.0
Interrupts are generated by the GPIO/DAC pins, the internal timers, I
USB traffic conditions. All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable
Register. Writing a ‘1’ to a bit position enables the interrupt associated with that bit position.
Global Interrupt Enable Register
Bit 0 : USB Bus RST Interrupt Enable
Bit 1 :128-µs Interrupt Enable
Bit 2 : 1.024-ms Interrupt Enable
Bit 3 : Reserved
Bit 4 : DAC Interrupt Enable
Bit 5 : GPIO Interrupt Enable
Bit 6 : I
Bit 7 : Reserved
USB Endpoint Interrupt Enable
Bit 0: EPA0 Interrupt Enable
Bit 1: EPA1 Interrupt Enable
Bit 2: EPA2 Interrupt Enable
Bit 3: EPB0 Interrupt Enable
Bit 4: EPB1 Interrupt Enable
Bit [7..5] : Reserved
During a reset, the contents the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared,
effectively, disabling all interrupts
Document #: 38-08001 Rev. *A
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
1= Enable Interrupt on a USB Bus Reset; 0 = Disable interrupt on a USB Bus Reset (Refer to section 16.3)
1 = Enable Timer interrupt every 128 µs; 0 = Disable Timer Interrupt for every 128 µs.
1= Enable Timer interrupt every 1.024 ms ; 0 = Disable Timer Interrupt every 1.024 ms.
1 = Enable Interrupt on falling/rising edge on any GPIO; 0 = Disable Interrupt on falling/rising edge on any GPIO (Refer to section
14.7, 9.1 and 9.2.)
1= Enable Interrupt on I2C related activity; 0 = Disable I2C related activity interrupt. (Refer to section 16.8).
1= Enable Interrupt on data activity through endpoint A0; 0= Disable Interrupt on data activity through endpoint A0
1= Enable Interrupt on data activity through endpoint A1; 0= Disable Interrupt on data activity through endpoint A1
1= Enable Interrupt on data activity through endpoint A2; 0= Disable Interrupt on data activity through endpoint A2.
1= Enable Interrupt on data activity through endpoint B0; 0= Disable Interrupt on data activity through endpoint B0
1= Enable Interrupt on data activity through endpoint B1; 0= Disable Interrupt on data activity through endpoint B1
1 = Enable DAC Interrupt; 0 = Disable DAC interrupt
2
C Interrupt Enable
Interrupts
Reserved
Reserved
7
-
-
7
-
-
I
2
Reserved
C Interrupt
Enable
R/W
6
0
6
-
-
Figure 16-2. USB Endpoint Interrupt Enable Register
Figure 16-1. Global Interrupt Enable Register
GPIO Interrupt
Reserved
Enable
R/W
5
0
5
-
-
EPB1 Interrupt
DAC Interrupt
enable
Enable
R/W
X
4
-
4
0
2
C-compatible interface or HAPI operation, or on various
EPB0 Interrupt
Reserved
Enable
R/W
R/W
3
0
3
0
Interrupt Enable
EPA2 Interrupt
1.024-ms
Enable
R/W
R/W
2
0
2
0
128-µs Interrupt
EPA1 Interrupt
Enable
Enable
R/W
R/W
1
0
1
0
CY7C64013
CY7C64113
Page 29 of 51
ADDRESS 0X20
ADDRESS 0X21
Interrupt Enable
EPA0 Interrupt
USB Bus RST
Enable
R/W
R/W
0
0
0
0