CY7C64013-SC Cypress Semiconductor Corp, CY7C64013-SC Datasheet - Page 36

• Manufacturer Part Number: CY7C64013-SC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013-SC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1327

Bit 7: Endpoint 0 SETUP Received
Bits[6:0] of the endpoint 0 mode register are locked from CPU write operations whenever the SIE has updated one of these bits,
which the SIE does only at the end of the token phase of a transaction (SETUP... Data... ACK, OUT... Data... ACK, or IN... Data...
ACK). The CPU can unlock these bits by doing a subsequent read of this register. Only endpoint 0 mode registers are locked
when updated. The locking mechanism does not apply to the mode registers of other endpoints.
Because of these hardware locking features, firmware must perform an IORD after an IOWR to an endpoint 0 register. This verifies
that the contents have changed as desired, and that the SIE has not updated these values.
While the SETUP bit is set, the CPU cannot write to the endpoint zero FIFOs. This prevents firmware from overwriting an incoming
SETUP transaction before firmware has a chance to read the SETUP data. Refer to Table 18-1 for the appropriate endpoint zero
memory locations.
The Mode bits (bits [3:0]) control how the endpoint responds to USB bus traffic. The mode bit encoding is shown inTable 19-1.
Additional information on the mode bits can be found inTable 19-2.
18.4
The format of the non-control endpoint mode register is shown in Figure 18-3.
Bits[3..0] : Mode
Bit 4 : ACK
Bits[6..5] : Reserved
Bit 7 : STALL
18.5
There are five Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as bits for data packet status. The format of these registers is shown
in Figure 18-4:
USB Endpoint Counter
Bits[5..0] : Byte Count
Bit 6 : Data Valid
Document #: 38-08001 Rev. *A
USB Non-Control Device Endpoint Mode
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
1= Token received is a SETUP token. 0= Token received is not a SETUP token. This bit is set ONLY by the SIE to report the type of
token received by the corresponding device address is a SETUP token. Any write to this bit by the CPU will clear it (set it to 0). The
bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the
SIE. The CPU should not clear this bit during this interval, and subsequently, until the CPU first does an IORD to this endpoint 0 mode
register. The bit must be cleared by firmware as part of the USB processing.
These sets the mode which control how the control endpoint responds to traffic. The mode bit encoding is shown in Table 19-1
This bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet.
Must be written zero during register writes.
These counter bits indicate the number of data bytes in a transaction. For IN transactions, firmware loads the count with the number of
bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 32, inclusive. For OUT or SETUP transactions, the
count is updated by hardware to the number of data bytes received, plus 2 for the CRC bytes. Valid values are 2 to 34, inclusive.
If this STALL is set, the SIE stalls an OUT packet if the mode bits are set to ACK-IN, and the SIE stalls an IN packet if the
mode bits are set to ACK-OUT. For all other modes, the STALL bit must be a LOW.
USB Non-Control Endpoint Mode Registers
USB Endpoint Counter Registers
Data 0/1 Toggle
STALL
R/W
R/W
7
0
7
0
Figure 18-3. USB Non-Control Device Endpoint Mode Registers
Data Valid
Reserved
R/W
R/W
6
0
6
0
Figure 18-4. USB Endpoint Counter Registers
Byte Count Bit 5 Byte Count Bit 4 Byte Count Bit 3 Byte Count Bit 2 Byte Count Bit 1 Byte Count Bit 0
Reserved
R/W
R/W
5
0
5
0
ACK
R/W
R/W
4
0
4
0
Mode Bit 3
R/W
R/W
3
0
3
0
Mode Bit 2
R/W
R/W
ADDRESSES
2
0
2
0
ADDRESSES 0x14, 0x16, 0x42
Mode Bit 1
0x11, 0x13, 0x15, 0x41, 0x43
R/W
R/W
1
0
1
0
CY7C64013
CY7C64113
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Mode Bit 0
R/W
R/W
0
0
0
0
,
0x44