CY7C64013-SC Cypress Semiconductor Corp, CY7C64013-SC Datasheet - Page 32

• Manufacturer Part Number: CY7C64013-SC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013-SC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1327

16.7
Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as
part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware needs to read the
GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt. A block diagram of the GPIO interrupt
logic is shown in Figure 16-4. Refer to Sections 9.1 and 9.2 for more information of setting GPIO interrupt polarity and enabling
individual GPIO interrupts.
If one port pin has triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive
(non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign interrupt priority
to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process.
When HAPI is enabled, the HAPI logic takes over the interrupt vector and blocks any interrupt from the GPIO bits, including
ports/bits not being used by HAPI. Operation of the HAPI interrupt is independent of the GPIO specific bit interrupt enables, and
is enabled or disabled only by bit 5 of the Global Interrupt Enable Register (Figure 16-1) when HAPI is enabled. The settings of
the GPIO bit interrupt enables on ports/bits not used by HAPI still effect the CMOS mode operation of those ports/bits. The effect
of modifying the interrupt bits while the Port Config bits are set to “10” is shown in Table 9-1. The events that generate HAPI
interrupts are described in Section 14.0.
16.8
The I
involves reading the I
I
interrupt indicates that status bits are stable and it is safe to read and write the I
the I
When enabled, the I
bits are in the I
Document #: 38-08001 Rev. *A
2
1. In slave receive mode, after the slave receives a byte of data: The Addr bit is set, if this is the first byte since a start or restart signal was
2. In slave receive mode, after a stop bit is detected: The Received Stop bit is set, if the stop bit follows a slave receive transaction where the
3. In slave transmit mode, after the slave transmits a byte of data: The ACK bit indicates if the master that requested the byte acknowledged
4. In master transmit mode, after the master sends a byte of data. Firmware should load the Data Register if necessary, and set the Xmit
C Data Register as appropriate, and finally writing the Status and Control Register to initiate the subsequent transaction. The
GPIO
Pin
sent by the external master. Firmware must read or write the data register as necessary, then set the ACK, Xmit MODE, and Continue/Busy
bits appropriately for the next byte.
ACK bit was cleared to 0, no stop bit detection occurs.
the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then sets the Xmit MODE and Continue/Busy
bits as required.
MODE, MSTR MODE, and Continue/Busy bits appropriately. Clearing the MSTR MODE bit issues a stop signal to the I
and return to the idle state.
2
IRA
2
C registers.
C interrupt occurs after various events on the I
1 = Enable
0 = Disable
GPIO/HAPI Interrupt
I
2
C Interrupt
2
C Status and Control Register.
2
C-compatible state machines generate interrupts on completion of the following conditions. The referenced
2
C Status and Control Register (Figure 13-2) to determine the cause of the interrupt, loading/reading the
Port Interrupt
Enable Register
Configuration
Register
M
U
X
Port
Figure 16-4. GPIO Interrupt Structure
1 = Enable
0 = Disable
2
C-compatible bus to signal the need for firmware interaction. This generally
(1 input per
GPIO pin)
OR Gate
(Bit 5, Register 0x20)
GPIO Interrupt
Global
Enable
1
GPIO Interrupt
Flip Flop
D
2
CLR
C registers. Refer to Section 13.0 for details on
Q
Interrupt
Encoder
Priority
CY7C64013
CY7C64113
2
C-compatible bus
Page 32 of 51
Interrupt
IRQout
Vector