CY7C64013-PC Cypress Semiconductor Corp, CY7C64013-PC Datasheet - Page 40

• Manufacturer Part Number: CY7C64013-PC
• Description: IC MCU 8K FULL SPEED USB 28DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013-PC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.300", 7.62mm)
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1326

An “Ignore” in any of the columns means that the device will not send any handshake tokens (no ACK) to the host.
An “Accept” in any of the columns means that the device will respond with an ACK to a valid SETUP transaction tot he host.
Comments
Some Mode Bits are automatically changed by the SIE in response to certain USB transactions. For example, if the Mode Bits
[3:0] are set to '1111' which is ACK IN-Status OUT mode as shown in table 22-1, the SIE will change the endpoint Mode Bits [3:0]
to NAK IN-Status OUT mode (1110) after ACK’ing a valid status stage OUT token. The firmware needs to update the mode for
the SIE to respond appropriately. See Table 18-1 for more details on what modes will be changed by the SIE. A disabled endpoint
will remain disabled until changed by firmware, and all endpoints reset to the disabled mode (0000). Firmware normally enables
the endpoint mode after a SetConfiguration request.
Any SETUP packet to an enabled endpoint with mode set to accept SETUPs will be changed by the SIE to 0001 (NAKing INs
and OUTs). Any mode set to accept a SETUP will send an ACK handshake to a valid SETUP token.
The control endpoint has three status bits for identifying the token type received (SETUP, IN, or OUT), but the endpoint must be
placed in the correct mode to function as such. Non-Control endpoints should not be placed into modes that accept SETUPs.
Note that most modes that control transactions involving an ending ACK, are changed by the SIE to a corresponding mode which
NAKs subsequent packets following the ACK. Exceptions are modes 1010 and 1110.
Note: The SIE offers an “Ack out–Status in” mode and not an “Ack out–Nak in” mode. Therefore, if following the status stage of
a Control Write transfer a USB host were to immediately start the next transfer, the new Setup packet could override the data
payload of the data stage of the previous Control Write.
The response of the SIE can be summarized as follows:
Document #: 38-08001 Rev. *A
1. The SIE will only respond to valid transactions, and will ignore non-valid ones.
2. The SIE will generate an interrupt when a valid transaction is completed or when the FIFO is corrupted. FIFO corruption occurs during
3. An incoming Data packet is valid if the count is < Endpoint Size + 2 (includes CRC) and passes all error checking;
4. An IN will be ignored by an OUT configured endpoint and visa versa.
5. The IN and OUT PID status is updated at the end of a transaction.
6. The SETUP PID status is updated at the beginning of the Data packet phase.
7. The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that endpoint in which
3
Endpoint Mode
encoding
Legend:
an OUT or SETUP transaction to a valid internal address, that ends with a non-valid CRC.
an ACK is transferred. These registers are only unlocked by a CPU read of the register, which should be done by the firmware only after
the transaction is complete. This represents about a 1-µs window in which the CPU is locked from register writes to these USB registers.
2
1
0
Received Token
(SETUP/IN/OUT)
Token
TX : transmit
RX : receive
x: don’t care
count
The number of received bytes
available for Control endpoint only
Incoming Packets
Properties of
buffer
The quality status of the DMA buffer
UC : unchanged
TX0 :Transmit 0 length packet
dval
The validity of the received data
Changes to the Internal Register made by the SIE on receiving an incoming packet
DTOG
Data0/1 (bit7 Figure 17-4)
DVAL
Data Valid (bit 6, Figure 17-4)
COUNT
Byte Count (bits 0..5, Figure 17-4)
from the host
Setup
(Bit[7..5], Figure 17-2)
PID Status Bits
In
Out
ACK
Acknowledge phase completed
3
2 1 0 Response
Changed by the SIE
Endpoint Mode bits
CY7C64013
CY7C64113
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SIE’s Response
to the Host
Interrupt
Int