AN2131QC Cypress Semiconductor Corp, AN2131QC Datasheet - Page 184

• Manufacturer Part Number: AN2131QC
• Description: IC MCU 8051 8K RAM 24MHZ 80BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2131QC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1307

section, this particular reset is called an “8051 Reset,” and should not be confused with the
POR described in Section 10.2, "EZ-USB Power-On Reset (POR)." This discussion
applies only to the condition where the EZ-USB chip is powered, and the 8051 is reset by
the host setting the CPUCS register to 0.
The basic USB device configuration remains intact through an 8051 reset. Valid end-
points remain valid, the USB function address remains the same, and the IO ports retain
their configurations and values. Stalled endpoints remain stalled, and data toggles don’t
change. The only effects of an 8051 reset are as follows:
The ReNum bit is not affected by an 8051 reset.
When the 8051 comes out of reset, the pending interrupts are kept pending, but disabled
(1). This gives the firmware writer the choice of acting on pre-8051-reset USB events, or
ignoring them by clearing the pending interrupt(s).
During the 8051 reset time, the EZ-USB core holds off any USB traffic by NAKing IN
and OUT tokens (2). The EZ-USB core automatically arms the OUT endpoints when the
8051 exits the reset state (3).
USBBAV.3, the breakpoint BREAK bit, is cleared (4). The other bits in the USBBAV reg-
ister are unaffected.
The host signals a USB Bus Reset by driving an SE0 state (both D+ and D- data lines low)
for a minimum of 10 ms. The EZ-USB core senses this condition, requests the 8051 USB
Interrupt (INT2), and supplies the interrupt vector for a USB Reset. A USB reset affects
the EZ-USB resources as shown in Table 10-2.
EZ-USB TRM v1.9
10.5
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•
•
•
USB interrupts are disabled, but pending interrupt requests remain pending.
During the 8051 Reset, all bulk endpoints are unarmed, causing the EZ-USB core
to NAK and IN or OUT tokens.
After the 8051 Reset is removed, the OUT bulk endpoints are automatically
armed. OUT endpoints are thus ready to accept one OUT packet before 8051
intervention is required.
The breakpoint condition is cleared.
USB Bus Reset
Chapter 10. EZ-USB Resets
Page 10-5