AN2131QC Cypress Semiconductor Corp, AN2131QC Datasheet - Page 124

• Manufacturer Part Number: AN2131QC
• Description: IC MCU 8051 8K RAM 24MHZ 80BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2131QC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1307

The STATUS stage consists of an empty data packet with the opposite direction of the data
stage, or an IN if there was no data stage. This empty data packet gives the device a
chance to ACK or NAK the entire CONTROL transfer. The 8051 writes a “1” to a bit call
HSNAK (Handshake NAK) to clear it and instruct the EZ-USB core to ACK the STATUS
stage.
The HSNAK bit is used to hold off completing the CONTROL transfer until the device
has had time to respond to a request. For example, if the host issues a Set_Interface
request, the 8051 performs various housekeeping chores such as adjusting internal modes
and re-initializing endpoints. During this time the host issues handshake (STATUS stage)
packets to which the EZ-USB core responds with NAKs, indicating “busy.” When the
8051 completes the desired operation, it sets HSNAK=1 (by writing a “1” to the bit) to ter-
minate the CONTROL transfer. This handshake prevents the host from attempting to use
a partially configured interface.
To perform an endpoint stall for the DATA or STATUS stage of an endpoint zero transfer
(the SETUP stage can never stall), the 8051 must set both the STALL and HSNAK bits for
endpoint zero.
Some CONTROL transfers do not have a DATA stage. Therefore the 8051 code that pro-
cesses the SETUP data should check the length field in the SETUP data (in the 8-byte
buffer at SETUPDAT) and arm endpoint zero for the DATA phase (by loading IN0BC or
OUT0BC) only if the length is non-zero.
Two 8051 interrupts provide notification that a SETUP packet has arrived, as shown in
Figure 7-2.
The EZ-USB core sets the SUTOKIR bit (SETUP Token Interrupt Request) when the EZ-
USB core detects the SETUP token at the beginning of a CONTROL transfer. This inter-
rupt is normally used only for debug.
The EZ-USB core sets the SUDAVIR bit (Setup Data Available Interrupt Request) when
the eight bytes of SETUP data have been received error-free and transferred to eight EZ-
EZ-USB TRM v1.9
Figure 7-2. The Two Interrupts Associated with EP0 CONTROL Transfers
Token Packet
S
E
T
U
P
A
D
D
R
Interrupt
SUTOK
E
N
D
P
SETUP Stage
C
R
C
5
D
A
T
A
0
Data Packet
8 bytes
Setup
Data
Chapter 7. EZ-USB CPU
C
R
C
1
6
H/S Pkt
Interrupt
SUDAV
A
C
K
8 RAM
bytes
SETUPDAT
Page 7-3