PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 410
PNX1502E,557
Manufacturer Part Number
PNX1502E,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Not Compliant
Other names
935274744557
PNX1502E
PNX1502E
PNX1502E
PNX1502E
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PNX1502E,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Philips Semiconductors
Volume 1 of 1
Table 20: QVCP 1 Registers
PNX15XX_SER_3
Product data sheet
Bit
11:0
Offset 0x10 E238
31:24
23:16
15:8
7:3
2:1
0
Offset 0x10 E23C
31:6
5
4
3
Symbol
LayerNWidth
Pedestal_up
Pedestal_mid
Pedestal_low
Unused
OP_format
FRMT_4xx
Unused
Buffer toggle
Layer_Start_Field
Premult
Pedestal and O/P format
Layer Pixel Processing
…Continued
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
-
0
0
-
0
1
0
Value
Rev. 3 — 17 March 2006
Description
initial (before scaling) Layer N width, in pixels.
Pedestal to be added to Upper input
(pedestal_up is a 2’s complement number from -128 to 127)
The pedestal removal is performed after the color key unit, before
dithering.
Pedestal to be added to Middle input
(pedestal_mid is a 2’s complement number from -128 to 127)
The pedestal removal is performed after the color key unit, before
dithering
Pedestal to be added to Lower input
(pedestal_low is a 2’s complement number from -128 to 127)
The pedestal removal is performed after the color key unit, before
dithering
Output type selector
Input format indicator
This bit controls the DMA buffer mode:
Field in which the layer gets actually enabled once the
LayerN_Enable bit is set. This bit is used to invert the internal odd/
even signal. If the result of the operation Layer_Start_Field xor OE
is true the layer is enabled, otherwise the layer stays disabled until
the OE signal changes.
In non-interlaced modes:
this bit must be set to 1’b1 since the internal odd/even signal is
forced to zero.
In interlaced modes:
LayerNStartY (0x10,E230) >= 0, set this bit to 0
LayerNStartY (0x10,E230) < 0, set this bit to 1
If this bit is set, the incoming pixels are premultiplied with alpha.
That disables the new x alpha multiplication in the mixer stage if
alpha blending is enabled.
0 = data expansion from 8 to 9 bit through multiply by two (zero in
LSB)
1 = data expansion from 8 to 9 bit through multiply by two (MSB
in LSB position)
2,3 = data expansion from 8 to 9 bit through multiply by two
(undither operation)
0 = Input is in 4:4:4 format
1 = Input is in 4:2:2 format
1 = Always toggle between buffer A and B (A=odd field, B=even
field).
0 = No buffer toggle, always fetch from buffer spec A.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 11: QVCP
11-57
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