STA2062A STMicroelectronics, STA2062A Datasheet

STA2062A

Manufacturer Part Number

STA2062A

Description

APPLICATION PROCESSOR 361-LFBGA

Manufacturer

STMicroelectronics

Datasheet

1.STA2062A.pdf (5 pages)

Specifications of STA2062A

Applications

GPS

Core Processor

ARM9

Program Memory Type

ROM (48 kB)

Controller Series

Cartesio™

Ram Size

160K x 8

Interface

CAN, I²C, IrDA, Microwire, MMC, MSP, SPI, SSI, SSP, UART/USART, USB, USB OTG

Number Of I /o

128

Voltage - Supply

1.08 V ~ 1.32 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

361-FBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Current page: 1 of 5
Download datasheet (146Kb)

Features

■

April 2008

For further information contact your local STMicroelectronics sales office.

High performance ARM926 MCU (up to 333 MHz)

MCU memory organization

– Cache: 16 Kbyte instruction, 16 Kbyte data

– 8 Kbyte instruction TCM (tightly coupled

– 8 Kbyte data TCM

– 32 Kbyte embedded ROM for boot

– Two banks of 64 Kbyte embedded SRAM

– 512 Byte embedded SRAM for back-up

– 4 Gbyte total linear address space

– Memory extension through:

Interrupt

– 64-channel interrupt controller (VIC)

– 16-vectorized interrupts with 16

DMA

– Two 8-channel double port system DMA

– 32 DMA request for each controller

– Two external DMA requests are supported

32-channel high performance GPS correlation

embedded subsystem

Eight 32-bit free running timers/counters

Four 16-bit extended function timer (EFT) with

input capture/output compare and PWM

Real-time clock (RTC)

Pulse width light modulator (PWL)

32-bit watchdog timer

Four autobaud UART with 64X8 transmit and

64x12 receive FIFO with DMA and hardware

flow control

One IrDA(SIR/MIR/FIR) interface

Three I

Two synchronous serial port (SSP) with 32x32

separate transmit and receive FIFO with

memory)

Flexible static memory controller-FSMC

(NOR/NAND Flash, CF/CF+, ROM, SRAM

support)

Mobile DDR/SDRAM controller:

16 bit data @166 MHz, 2 Chip Select,

512 Kbit each

programmable priority level

controllers

C multi-master/slave interfaces

infotainment application processor with embedded GPS

Rev 1

■

Table 1.

Order code

Motorola-SPI, National-MICROWIRE and

Texas- SSI support modes

Four multichannel serial ports (MSP) with 32x8

separate transmit and receive FIFO

Color LCD controller for STN,TFT or HR-TFT

panels

USB 2.0 OTG high speed dual role controller

(ULPI interface)

USB full speed dual role controller with

integrated 1.1 physical layer transceiver

Two secure-digital multimedia memory card

interface (SD/SDIO/MMC) up to 8 bit data

SPDIF input interface

C3 hardware Reed-Solomon decoder

Hardware sample rate converter (SaRaC)

Two controller area network (CAN)

Four 32-bit GPIO ports

JTAG based in-circuit emulator (ICE) with

embedded medium trace module

Typical working condition: V

Overdrive: V

2.5 V ±10%

Bus frequency: 166 MHz (overdrive)

Bus/DDR frequency: 166 MHz

HCMOS 0.90 µm process

Package:

– LFBGA16x16x1.4 mm (19x19 balls)

– 0.8 mm ball pitch, (0.4 mm ball)

– Full array

Ambient temperature range: -40 / +85 °C

STA2062A

: 1.8 V

LFBGA361 (16x16x1.4mm)

Device summary

: 1.4 V ±5%, V

LFBGA361

Package

Cartesio™ family

STA2062A

: 1.2 V ±10%,

: 1.8 V ±10%,

Packing

Tray

Data Brief

www.st.com

1/5

Related parts for STA2062A

STA2062A Summary of contents

Page 1

... Package: – LFBGA16x16x1.4 mm (19x19 balls) – 0.8 mm ball pitch, (0.4 mm ball) – Full array ■ Ambient temperature range: -40 / +85 °C Table 1. Device summary Order code Package STA2062A LFBGA361 Rev 1 STA2062A Data Brief : 1.2 V ±10 1.8 V ±10%, IO Packing Tray 1/5 www.st.com 5 ...

Page 2

... Description 1 Description The STA2062A is an highly integrated SoC application processor combining host capability with embedded GPS. STA2062A targets vehicles and personal mobile navigation (PND), telematics, advance audio and connectivity systems. Figure 1: Block diagram ARM926 microcontroller and its peripherals are interfaced. Block diagram Figure 1 ...

Page 3

... STA2062A 2 Package information In order to meet environmental requirements, ST offers this device in ECOPACK This package has a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

Page 4

... Revision history 3 Revision history Table 2. Document revision history Date 16-Apr-2008 4/5 Revision 1 Initial release. STA2062A Changes ...

Page 5

... STA2062A Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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