XE8806AMI026TLF Semtech, XE8806AMI026TLF Datasheet - Page 18

• Manufacturer Part Number: XE8806AMI026TLF
• Description: IC MCU LOW PWR MTP FLASH 32-TQFP
• Manufacturer: Semtech

Specifications of XE8806AMI026TLF

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 512 x 8
• Interface: UART, USRT
• Number Of I /o: 24
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: XE8806AMI026TR

3.1
The CPU of the XE8000 series is a low power RISC core. It has 16 internal registers for efficient implementation of
the C compiler. Its instruction set is made up of 35 generic instructions, all coded on 22 bits, with 8 addressing
modes. All instructions are executed in one clock cycle, including conditional jumps and 8x8 multiplication. The
circuit therefore runs on 1 MIPS on a 1MHz clock.
The CPU hardware and software description is given in the document “Coolrisc816 Hardware and Software
Reference Manual”. A short summary is given in the following paragraphs.
The
compiler, all numbers are signed integers on 16 bits).
3.2
As shown in Figure 3-1, the CPU has 16 internal 8-bit registers. Some of these registers can be concatenated to a
16-bit word for use in some instructions. The function of these registers is defined in Table 3-1. The status register
stat (Table 3-2) is used to manage the different interrupt and event levels. An interrupt or an event can both be
used to wake up after a HALT instruction. The difference is that an interrupt jumps to a special interrupt function
whereas an event continues the software execution with the instruction following the HALT instruction.
The program counter (PC) is a 16 bit register that indicates the address of the instruction that has to be executed.
The stack (ST
Figure 3-1. CPU internal registers
© Semtech 2006
Z
=
Instruction
(
good
A
memory
CPU description
0
CPU internal registers
22bit
+
A
1
code efficiency of the CPU
n
⋅
) is used to memorise the return address when executing subroutines or interrupt routines.
Y
)
⋅
X
+
B
0
+
B
1
⋅
Y
in less than 300 clock cycles (software code generated by the XEMICS C-
program counter stack
stat
i0h
i1h
i2h
i3h
iph
r0
r1
r2
r3
a
CPU
core makes it possible to compute
i0l
i1l
i2l
i3l
ipl
3-2
Data memory
XE8806A/XE8807A
a polynomial like
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