CY7C63413-PVC Cypress Semiconductor Corp, CY7C63413-PVC Datasheet - Page 4

• Manufacturer Part Number: CY7C63413-PVC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413-PVC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1319

Figure 6-1. Program Memory Space with Interrupt Vector Table ......................................................... 11
Figure 7-1. Clock Oscillator On-chip Circuit .......................................................................................... 14
Figure 8-1. Watch Dog Reset (WDR) ................................................................................................... 15
Figure 9-1. Block Diagram of a GPIO Line ........................................................................................... 15
Figure 9-2. Port 0 Data 0x00h (read/write) ........................................................................................... 16
Figure 9-3. Port 1 Data 0x01h (read/write) ........................................................................................... 16
Figure 9-4. Port 2 Data 0x02h (read/write) ........................................................................................... 16
Figure 9-5. Port 3 Data 0x03h (read/write) ........................................................................................... 16
Figure 9-6. Port 0 Interrupt Enable 0x04h (write only) .......................................................................... 16
Figure 9-7. Port 1 Interrupt Enable 0x05h (write only) .......................................................................... 16
Figure 9-8. Port 2 Interrupt Enable 0x06h (write only) .......................................................................... 16
Figure 9-9. Port 3 Interrupt Enable 0x07h (write only) .......................................................................... 16
Figure 9-10. GPIO Configuration Register 0x08h (write only) .............................................................. 17
Figure 10-1. Block Diagram of DAC Port .............................................................................................. 17
Figure 10-2. DAC Port Data 0x30h (read/write) .................................................................................... 18
Figure 10-3. DAC Port Interrupt Enable 0x31h (write only) .................................................................. 18
Figure 10-4. DAC Port Interrupt Polarity 0x32h (write only) ................................................................. 18
Figure 10-5. DAC Port Isink 0x38h to 0x3Fh (write only) ..................................................................... 18
Figure 11-1. USB Status and Control Register 0x1Fh .......................................................................... 19
Figure 12-1. USB Device Address Register 0x10h (read/write) ........................................................... 20
Figure 12-2. USB Device EPA0 Mode Register 0x12h (read/write) ..................................................... 20
Figure 12-3. USB Device Endpoint Mode Registers 0x14h, 0x16h (read/write) ................................... 20
Figure 12-4. USB Device Counter Registers 0x11h, 0x13h, 0x15h (read/write) .................................. 21
Figure 13-1. Timer Register 0x24h (read only) ..................................................................................... 21
Figure 13-2. Timer Register 0x25h (read only) ..................................................................................... 21
Figure 13-3. Timer Block Diagram ........................................................................................................ 21
Figure 14-1. Processor Status and Control Register 0xFFh ................................................................. 22
Figure 15-1. Global Interrupt Enable Register 0x20h (read/write) ........................................................ 22
Figure 15-2. USB End Point Interrupt Enable Register 0x21h (read/write) .......................................... 23
Figure 19-1. Clock Timing ..................................................................................................................... 29
Figure 19-2. USB Data Signal Timing ................................................................................................... 30
Figure 19-3. Receiver Jitter Tolerance ................................................................................................. 30
Figure 19-4. Differential to EOP Transition Skew and EOP Width ....................................................... 30
Figure 19-5. Differential Data Jitter ....................................................................................................... 31
Table 6-1. I/O Register Summary ........................................................................................................ 13
Table 15-1. Interrupt Vector Assignments ........................................................................................... 23
Table 16-1. USB Register Mode Encoding .......................................................................................... 24
Table 16-2. Decode table for Table 16-3 : “Details of Modes for Differing Traffic Conditions” .............. 25
Table 16-3. Details of Modes for Differing Traffic Conditions .............................................................. 26
LIST OF FIGURES
LIST OF TABLES
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CY7C63411/12/13
CY7C63511/12/13